arch/arm64/boot/dts/marvell/armada-7040.dtsi
Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/marvell/armada-7040.dtsi
File Facts
- System
- Linux kernel
- Corpus path
arch/arm64/boot/dts/marvell/armada-7040.dtsi- Extension
.dtsi- Size
- 569 bytes
- Lines
- 35
- Domain
- Architecture Layer
- Bucket
- arch/arm64
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
armada-ap806-quad.dtsiarmada-70x0.dtsi
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2016 Marvell Technology Group Ltd.
*
* Device Tree file for the Armada 7040 SoC, made of an AP806 Quad and
* one CP110.
*/
#include "armada-ap806-quad.dtsi"
#include "armada-70x0.dtsi"
&cp0_pcie0 {
iommu-map =
<0x0 &smmu 0x480 0x20>,
<0x100 &smmu 0x4a0 0x20>,
<0x200 &smmu 0x4c0 0x20>;
iommu-map-mask = <0x031f>;
};
&cp0_sata0 {
iommus = <&smmu 0x444>;
};
&cp0_sdhci0 {
iommus = <&smmu 0x445>;
};
&cp0_usb3_0 {
iommus = <&smmu 0x440>;
};
&cp0_usb3_1 {
iommus = <&smmu 0x441>;
};
Annotation
- Immediate include surface: `armada-ap806-quad.dtsi`, `armada-70x0.dtsi`.
- Atlas domain: Architecture Layer / arch/arm64.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.