arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi

Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi

File Facts

System
Linux kernel
Corpus path
arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi
Extension
.dtsi
Size
2070 bytes
Lines
95
Domain
Architecture Layer
Bucket
arch/arm64
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (C) 2016 Marvell Technology Group Ltd.
 *
 * Device Tree file for Marvell Armada AP806.
 */

#include "armada-ap806.dtsi"

/ {
	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a72";
			reg = <0x000>;
			enable-method = "psci";
			#cooling-cells = <2>;
			clocks = <&cpu_clk 0>;
			i-cache-size = <0xc000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <256>;
			next-level-cache = <&l2_0>;
		};
		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a72";
			reg = <0x001>;
			enable-method = "psci";
			#cooling-cells = <2>;
			clocks = <&cpu_clk 0>;
			i-cache-size = <0xc000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <256>;
			next-level-cache = <&l2_0>;
		};
		cpu2: cpu@100 {
			device_type = "cpu";
			compatible = "arm,cortex-a72";
			reg = <0x100>;
			enable-method = "psci";
			#cooling-cells = <2>;
			clocks = <&cpu_clk 1>;
			i-cache-size = <0xc000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <256>;
			next-level-cache = <&l2_1>;
		};
		cpu3: cpu@101 {
			device_type = "cpu";
			compatible = "arm,cortex-a72";
			reg = <0x101>;
			enable-method = "psci";
			#cooling-cells = <2>;
			clocks = <&cpu_clk 1>;
			i-cache-size = <0xc000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;

Annotation

Implementation Notes