arch/arm64/boot/dts/marvell/armada-ap810-ap0.dtsi
Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/marvell/armada-ap810-ap0.dtsi
File Facts
- System
- Linux kernel
- Corpus path
arch/arm64/boot/dts/marvell/armada-ap810-ap0.dtsi- Extension
.dtsi- Size
- 2749 bytes
- Lines
- 123
- Domain
- Architecture Layer
- Bucket
- arch/arm64
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
dt-bindings/interrupt-controller/arm-gic.h
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2017 Marvell Technology Group Ltd.
*
* Device Tree file for Marvell Armada AP810.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
/dts-v1/;
/ {
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&gic>;
aliases {
serial0 = &uart0_ap0;
serial1 = &uart1_ap0;
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
};
soc {
#address-cells = <2>;
#size-cells = <2>;
compatible = "simple-bus";
ranges;
bus@e8000000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges = <0x0 0x0 0xe8000000 0x4000000>;
interrupt-parent = <&gic>;
gic: interrupt-controller@3000000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
#address-cells = <1>;
#size-cells = <1>;
interrupt-controller;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
ranges;
reg = <0x3000000 0x10000>, /* GICD */
<0x3060000 0x100000>, /* GICR */
<0x00c0000 0x2000>, /* GICC */
<0x00d0000 0x1000>, /* GICH */
<0x00e0000 0x2000>; /* GICV */
gic_its_ap0: msi-controller@3040000 {
compatible = "arm,gic-v3-its";
msi-controller;
#msi-cells = <1>;
reg = <0x3040000 0x20000>;
};
};
Annotation
- Immediate include surface: `dt-bindings/interrupt-controller/arm-gic.h`.
- Atlas domain: Architecture Layer / arch/arm64.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.