arch/arm64/boot/dts/marvell/cn9130-cf.dtsi
Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/marvell/cn9130-cf.dtsi
File Facts
- System
- Linux kernel
- Corpus path
arch/arm64/boot/dts/marvell/cn9130-cf.dtsi- Extension
.dtsi- Size
- 4011 bytes
- Lines
- 199
- Domain
- Architecture Layer
- Bucket
- arch/arm64
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2024 Josua Mayer <josua@solid-run.com>
*
* DTS for common base of SolidRun CN9130 Clearfog Base and Pro.
*
*/
/ {
aliases {
/* label nics same order as armada 388 clearfog */
ethernet0 = &cp0_eth2;
ethernet1 = &cp0_eth1;
ethernet2 = &cp0_eth0;
i2c1 = &cp0_i2c1;
mmc1 = &cp0_sdhci0;
};
reg_usb3_vbus0: regulator-usb3-vbus0 {
compatible = "regulator-fixed";
regulator-name = "vbus0";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpios = <&expander0 6 GPIO_ACTIVE_LOW>;
};
sfp: sfp {
compatible = "sff,sfp";
i2c-bus = <&cp0_i2c1>;
los-gpios = <&expander0 12 GPIO_ACTIVE_HIGH>;
mod-def0-gpios = <&expander0 15 GPIO_ACTIVE_LOW>;
tx-disable-gpios = <&expander0 14 GPIO_ACTIVE_HIGH>;
tx-fault-gpios = <&expander0 13 GPIO_ACTIVE_HIGH>;
maximum-power-milliwatt = <2000>;
};
};
/* SRDS #2 - SFP+ 10GE */
&cp0_eth0 {
managed = "in-band-status";
phys = <&cp0_comphy2 0>;
phy-mode = "10gbase-r";
sfp = <&sfp>;
status = "okay";
};
&cp0_i2c0 {
expander0: gpio-expander@20 {
compatible = "nxp,pca9555";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
pinctrl-0 = <&expander0_pins>;
pinctrl-names = "default";
interrupt-parent = <&cp0_gpio1>;
interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
/* CON3 */
pcie2-0-clkreq-hog {
gpio-hog;
gpios = <0 GPIO_ACTIVE_LOW>;
input;
line-name = "pcie2.0-clkreq";
};
/* CON3 */
pcie2-0-w-disable-hog {
gpio-hog;
gpios = <3 GPIO_ACTIVE_LOW>;
output-low;
Annotation
- Atlas domain: Architecture Layer / arch/arm64.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.