arch/arm64/boot/dts/marvell/cn9131-cf-solidwan.dts
Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/marvell/cn9131-cf-solidwan.dts
File Facts
- System
- Linux kernel
- Corpus path
arch/arm64/boot/dts/marvell/cn9131-cf-solidwan.dts- Extension
.dts- Size
- 12741 bytes
- Lines
- 642
- Domain
- Architecture Layer
- Bucket
- arch/arm64
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
dt-bindings/input/input.hdt-bindings/leds/common.hcn9130.dtsicn9130-sr-som.dtsiarmada-cp115.dtsi
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2024 Josua Mayer <josua@solid-run.com>
*
* DTS for SolidRun CN9130 Clearfog Base.
*
*/
/dts-v1/;
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
#include "cn9130.dtsi"
#include "cn9130-sr-som.dtsi"
/*
* Instantiate the external CP115
*/
#define CP11X_NAME cp1
#define CP11X_BASE f4000000
#define CP11X_PCIEx_MEM_BASE(iface) (0xe2000000 + (iface * 0x1000000))
#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
#define CP11X_PCIE0_BASE f4600000
#define CP11X_PCIE1_BASE f4620000
#define CP11X_PCIE2_BASE f4640000
#include "armada-cp115.dtsi"
#undef CP11X_NAME
#undef CP11X_BASE
#undef CP11X_PCIEx_MEM_BASE
#undef CP11X_PCIEx_MEM_SIZE
#undef CP11X_PCIE0_BASE
#undef CP11X_PCIE1_BASE
#undef CP11X_PCIE2_BASE
/ {
model = "SolidRun CN9131 SolidWAN";
compatible = "solidrun,cn9131-solidwan",
"solidrun,cn9130-sr-som", "marvell,cn9130";
aliases {
ethernet0 = &cp1_eth1;
ethernet1 = &cp1_eth2;
ethernet2 = &cp0_eth1;
ethernet3 = &cp0_eth2;
ethernet4 = &cp0_eth0;
ethernet5 = &cp1_eth0;
gpio0 = &ap_gpio;
gpio1 = &cp0_gpio1;
gpio2 = &cp0_gpio2;
gpio3 = &cp1_gpio1;
gpio4 = &cp1_gpio2;
gpio5 = &expander0;
i2c0 = &cp0_i2c0;
i2c1 = &cp0_i2c1;
i2c2 = &cp1_i2c1;
mmc0 = &ap_sdhci0;
mmc1 = &cp0_sdhci0;
rtc0 = &cp0_rtc;
rtc1 = &carrier_rtc;
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&cp0_led_pins &cp1_led_pins>;
Annotation
- Immediate include surface: `dt-bindings/input/input.h`, `dt-bindings/leds/common.h`, `cn9130.dtsi`, `cn9130-sr-som.dtsi`, `armada-cp115.dtsi`.
- Atlas domain: Architecture Layer / arch/arm64.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.