arch/arm64/boot/dts/marvell/cn9131-db.dtsi

Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/marvell/cn9131-db.dtsi

File Facts

System
Linux kernel
Corpus path
arch/arm64/boot/dts/marvell/cn9131-db.dtsi
Extension
.dtsi
Size
4262 bytes
Lines
207
Domain
Architecture Layer
Bucket
arch/arm64
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (C) 2020 Marvell International Ltd.
 *
 * Device tree for the CN9131-DB board.
 */

#include "cn9130-db.dtsi"

/ {
	compatible = "marvell,cn9131", "marvell,cn9130",
		     "marvell,armada-ap807-quad", "marvell,armada-ap807";

	aliases {
		gpio3 = &cp1_gpio1;
		gpio4 = &cp1_gpio2;
		ethernet3 = &cp1_eth0;
		ethernet4 = &cp1_eth1;
	};

	cp1_reg_usb3_vbus0: regulator-6 {
		compatible = "regulator-fixed";
		pinctrl-names = "default";
		pinctrl-0 = <&cp1_xhci0_vbus_pins>;
		regulator-name = "cp1-xhci0-vbus";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		enable-active-high;
		gpio = <&cp1_gpio1 3 GPIO_ACTIVE_HIGH>;
	};

	cp1_usb3_0_phy0: usb-phy-3 {
		compatible = "usb-nop-xceiv";
		#phy-cells = <0>;
		vcc-supply = <&cp1_reg_usb3_vbus0>;
	};

	cp1_sfp_eth1: sfp-eth-2 {
		compatible = "sff,sfp";
		i2c-bus = <&cp1_i2c0>;
		los-gpios = <&cp1_gpio1 11 GPIO_ACTIVE_HIGH>;
		mod-def0-gpios = <&cp1_gpio1 10 GPIO_ACTIVE_LOW>;
		tx-disable-gpios = <&cp1_gpio1 9 GPIO_ACTIVE_HIGH>;
		tx-fault-gpios = <&cp1_gpio1 8 GPIO_ACTIVE_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&cp1_sfp_pins>;
		/*
		 * SFP cages are unconnected on early PCBs because of an the I2C
		 * lanes not being connected. Prevent the port for being
		 * unusable by disabling the SFP node.
		 */
		status = "disabled";
	};
};

/*
 * Instantiate the first slave CP115
 */

#define CP11X_NAME		cp1
#define CP11X_BASE		f4000000
#define CP11X_PCIEx_MEM_BASE(iface) (0xe2000000 + (iface * 0x1000000))
#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
#define CP11X_PCIE0_BASE	f4600000
#define CP11X_PCIE1_BASE	f4620000
#define CP11X_PCIE2_BASE	f4640000

#include "armada-cp115.dtsi"

#undef CP11X_NAME

Annotation

Implementation Notes