arch/arm64/boot/dts/marvell/cn9132-sr-cex7.dtsi

Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/marvell/cn9132-sr-cex7.dtsi

File Facts

System
Linux kernel
Corpus path
arch/arm64/boot/dts/marvell/cn9132-sr-cex7.dtsi
Extension
.dtsi
Size
13689 bytes
Lines
721
Domain
Architecture Layer
Bucket
arch/arm64
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (C) 2024 Josua Mayer <josua@solid-run.com>
 *
 */

#include <dt-bindings/gpio/gpio.h>

/*
 * Instantiate the first external CP115
 */

#define CP11X_NAME		cp1
#define CP11X_BASE		f4000000
#define CP11X_PCIEx_MEM_BASE(iface) (0xe2000000 + (iface * 0x1000000))
#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
#define CP11X_PCIE0_BASE	f4600000
#define CP11X_PCIE1_BASE	f4620000
#define CP11X_PCIE2_BASE	f4640000

#include "armada-cp115.dtsi"

#undef CP11X_NAME
#undef CP11X_BASE
#undef CP11X_PCIEx_MEM_BASE
#undef CP11X_PCIEx_MEM_SIZE
#undef CP11X_PCIE0_BASE
#undef CP11X_PCIE1_BASE
#undef CP11X_PCIE2_BASE

/*
 * Instantiate the second external CP115
 */

#define CP11X_NAME		cp2
#define CP11X_BASE		f6000000
#define CP11X_PCIEx_MEM_BASE(iface) (0xe5000000 + (iface * 0x1000000))
#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
#define CP11X_PCIE0_BASE	f6600000
#define CP11X_PCIE1_BASE	f6620000
#define CP11X_PCIE2_BASE	f6640000

#include "armada-cp115.dtsi"

#undef CP11X_NAME
#undef CP11X_BASE
#undef CP11X_PCIEx_MEM_BASE
#undef CP11X_PCIEx_MEM_SIZE
#undef CP11X_PCIE0_BASE
#undef CP11X_PCIE1_BASE
#undef CP11X_PCIE2_BASE

/ {
	model = "SolidRun CN9132 COM Express Type 7 Module";
	compatible = "solidrun,cn9132-sr-cex7", "marvell,cn9130";

	aliases {
		ethernet0 = &cp0_eth1;
		gpio3 = &cp1_gpio1;
		gpio4 = &cp1_gpio2;
		gpio5 = &cp2_gpio1;
		gpio6 = &cp2_gpio2;
		i2c0 = &cp0_i2c0;
		i2c1 = &cp0_i2c1;
		i2c2 = &com_clkgen_i2c;
		i2c3 = &com_10g_led_i2c;
		i2c4 = &com_10g_sfp_i2c0;
		i2c5 = &com_smbus;
		i2c6 = &com_fanctrl_i2c;
		mmc0 = &ap_sdhci0;

Annotation

Implementation Notes