arch/arm64/boot/dts/marvell/mmp/pxa1908.dtsi
Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/marvell/mmp/pxa1908.dtsi
File Facts
- System
- Linux kernel
- Corpus path
arch/arm64/boot/dts/marvell/mmp/pxa1908.dtsi- Extension
.dtsi- Size
- 8239 bytes
- Lines
- 353
- Domain
- Architecture Layer
- Bucket
- arch/arm64
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
dt-bindings/interrupt-controller/arm-gic.hdt-bindings/clock/marvell,pxa1908.hdt-bindings/power/marvell,pxa1908-power.h
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: GPL-2.0-only
/dts-v1/;
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/marvell,pxa1908.h>
#include <dt-bindings/power/marvell,pxa1908-power.h>
/ {
model = "Marvell Armada PXA1908";
compatible = "marvell,pxa1908";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&gic>;
cpus {
#address-cells = <2>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0 0>;
enable-method = "psci";
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0 1>;
enable-method = "psci";
};
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0 2>;
enable-method = "psci";
};
cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0 3>;
enable-method = "psci";
};
};
pmu {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
};
psci {
compatible = "arm,psci-0.2", "arm,psci";
method = "smc";
cpu_off = <0x85000001>;
cpu_on = <0x85000002>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
ramoops@8100000 {
Annotation
- Immediate include surface: `dt-bindings/interrupt-controller/arm-gic.h`, `dt-bindings/clock/marvell,pxa1908.h`, `dt-bindings/power/marvell,pxa1908-power.h`.
- Atlas domain: Architecture Layer / arch/arm64.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.