arch/arm64/boot/dts/mediatek/mt7988a.dtsi

Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/mediatek/mt7988a.dtsi

File Facts

System
Linux kernel
Corpus path
arch/arm64/boot/dts/mediatek/mt7988a.dtsi
Extension
.dtsi
Size
27394 bytes
Lines
1040
Domain
Architecture Layer
Bucket
arch/arm64
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0-only OR MIT

#include <dt-bindings/clock/mediatek,mt7988-clk.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/pinctrl/mt65xx.h>
#include <dt-bindings/reset/mediatek,mt7988-resets.h>

/ {
	compatible = "mediatek,mt7988a";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	cci: cci {
		compatible = "mediatek,mt7988-cci", "mediatek,mt8183-cci";
		clocks = <&mcusys CLK_MCU_BUS_DIV_SEL>,
			 <&topckgen CLK_TOP_XTAL>;
		clock-names = "cci", "intermediate";
		operating-points-v2 = <&cci_opp>;
	};

	cci_opp: opp-table-cci {
		compatible = "operating-points-v2";
		opp-shared;
		opp-480000000 {
			opp-hz = /bits/ 64 <480000000>;
			opp-microvolt = <850000>;
		};
		opp-660000000 {
			opp-hz = /bits/ 64 <660000000>;
			opp-microvolt = <850000>;
		};
		opp-900000000 {
			opp-hz = /bits/ 64 <900000000>;
			opp-microvolt = <850000>;
		};
		opp-1080000000 {
			opp-hz = /bits/ 64 <1080000000>;
			opp-microvolt = <900000>;
		};
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			compatible = "arm,cortex-a73";
			reg = <0x0>;
			device_type = "cpu";
			enable-method = "psci";
			clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
				 <&topckgen CLK_TOP_XTAL>;
			clock-names = "cpu", "intermediate";
			operating-points-v2 = <&cluster0_opp>;
			mediatek,cci = <&cci>;
		};

		cpu1: cpu@1 {
			compatible = "arm,cortex-a73";
			reg = <0x1>;
			device_type = "cpu";
			enable-method = "psci";
			clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
				 <&topckgen CLK_TOP_XTAL>;
			clock-names = "cpu", "intermediate";
			operating-points-v2 = <&cluster0_opp>;
			mediatek,cci = <&cci>;
		};

Annotation

Implementation Notes