arch/arm64/boot/dts/mediatek/mt8195.dtsi

Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/mediatek/mt8195.dtsi

File Facts

System
Linux kernel
Corpus path
arch/arm64/boot/dts/mediatek/mt8195.dtsi
Extension
.dtsi
Size
126626 bytes
Lines
4263
Domain
Architecture Layer
Bucket
arch/arm64
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Copyright (c) 2021 MediaTek Inc.
 * Author: Seiya Wang <seiya.wang@mediatek.com>
 */

/dts-v1/;
#include <dt-bindings/clock/mt8195-clk.h>
#include <dt-bindings/gce/mt8195-gce.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/memory/mt8195-memory-port.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/pinctrl/mt8195-pinfunc.h>
#include <dt-bindings/power/mt8195-power.h>
#include <dt-bindings/reset/mt8195-resets.h>
#include <dt-bindings/thermal/thermal.h>
#include <dt-bindings/thermal/mediatek,lvts-thermal.h>

/ {
	compatible = "mediatek,mt8195";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
		dp-intf0 = &dp_intf0;
		dp-intf1 = &dp_intf1;
		dpi1 = &dpi1;
		gce0 = &gce0;
		gce1 = &gce1;
		hdmi0 = &hdmi;
		ethdr0 = &ethdr0;
		mutex0 = &mutex;
		mutex1 = &mutex1;
		merge1 = &merge1;
		merge2 = &merge2;
		merge3 = &merge3;
		merge4 = &merge4;
		merge5 = &merge5;
		vdo1-rdma0 = &vdo1_rdma0;
		vdo1-rdma1 = &vdo1_rdma1;
		vdo1-rdma2 = &vdo1_rdma2;
		vdo1-rdma3 = &vdo1_rdma3;
		vdo1-rdma4 = &vdo1_rdma4;
		vdo1-rdma5 = &vdo1_rdma5;
		vdo1-rdma6 = &vdo1_rdma6;
		vdo1-rdma7 = &vdo1_rdma7;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a55";
			reg = <0x000>;
			enable-method = "psci";
			performance-domains = <&performance 0>;
			clock-frequency = <1701000000>;
			capacity-dmips-mhz = <308>;
			cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
			i-cache-size = <32768>;
			i-cache-line-size = <64>;
			i-cache-sets = <128>;
			d-cache-size = <32768>;
			d-cache-line-size = <64>;
			d-cache-sets = <128>;
			next-level-cache = <&l2_0>;

Annotation

Implementation Notes