arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk-ufs.dts
Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk-ufs.dts
File Facts
- System
- Linux kernel
- Corpus path
arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk-ufs.dts- Extension
.dts- Size
- 546 bytes
- Lines
- 30
- Domain
- Architecture Layer
- Bucket
- arch/arm64
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
mt8395-genio-common.dtsi
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2025 MediaTek Inc.
* Author: Ramax Lo <ramax.lo@mediatek.com>
* Macpaul Lin <macpaul.lin@mediatek.com>
*/
/dts-v1/;
#include "mt8395-genio-common.dtsi"
/ {
model = "MediaTek Genio 1200 EVK-P1V2-UFS";
compatible = "mediatek,mt8395-evk-ufs", "mediatek,mt8395",
"mediatek,mt8195";
};
&ufshci {
status = "okay";
vcc-supply = <&mt6359_vemc_1_ldo_reg>;
vccq2-supply = <&mt6359_vufs_ldo_reg>;
};
&ufsphy {
status = "okay";
};
&mmc0 {
status = "disabled";
};
Annotation
- Immediate include surface: `mt8395-genio-common.dtsi`.
- Atlas domain: Architecture Layer / arch/arm64.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.