arch/arm64/boot/dts/mediatek/mt8516.dtsi

Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/mediatek/mt8516.dtsi

File Facts

System
Linux kernel
Corpus path
arch/arm64/boot/dts/mediatek/mt8516.dtsi
Extension
.dtsi
Size
14498 bytes
Lines
542
Domain
Architecture Layer
Bucket
arch/arm64
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (c) 2019 MediaTek Inc.
 * Copyright (c) 2019 BayLibre, SAS.
 * Author: Fabien Parent <fparent@baylibre.com>
 */

#include <dt-bindings/clock/mt8516-clk.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/phy/phy.h>

#include "mt8516-pinfunc.h"

/ {
	compatible = "mediatek,mt8516";
	interrupt-parent = <&sysirq>;
	#address-cells = <2>;
	#size-cells = <2>;

	cluster0_opp: opp-table-0 {
		compatible = "operating-points-v2";
		opp-shared;
		opp-598000000 {
			opp-hz = /bits/ 64 <598000000>;
			opp-microvolt = <1150000>;
		};
		opp-747500000 {
			opp-hz = /bits/ 64 <747500000>;
			opp-microvolt = <1150000>;
		};
		opp-1040000000 {
			opp-hz = /bits/ 64 <1040000000>;
			opp-microvolt = <1200000>;
		};
		opp-1196000000 {
			opp-hz = /bits/ 64 <1196000000>;
			opp-microvolt = <1250000>;
		};
		opp-1300000000 {
			opp-hz = /bits/ 64 <1300000000>;
			opp-microvolt = <1300000>;
		};
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a35";
			reg = <0x0>;
			enable-method = "psci";
			cpu-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_0>,
				<&CPU_SLEEP_0_0 &CPU_SLEEP_0_0 &CPU_SLEEP_0_0>;
			clocks = <&infracfg CLK_IFR_MUX1_SEL>,
				 <&topckgen CLK_TOP_MAINPLL_D2>;
			clock-names = "cpu", "intermediate";
			operating-points-v2 = <&cluster0_opp>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a35";
			reg = <0x1>;
			enable-method = "psci";
			cpu-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_0>,
				<&CPU_SLEEP_0_0 &CPU_SLEEP_0_0 &CPU_SLEEP_0_0>;
			clocks = <&infracfg CLK_IFR_MUX1_SEL>,

Annotation

Implementation Notes