arch/arm64/boot/dts/microchip/sparx5_nand.dtsi
Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/microchip/sparx5_nand.dtsi
File Facts
- System
- Linux kernel
- Corpus path
arch/arm64/boot/dts/microchip/sparx5_nand.dtsi- Extension
.dtsi- Size
- 619 bytes
- Lines
- 32
- Domain
- Architecture Layer
- Bucket
- arch/arm64
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
*/
&gpio {
cs14_pins: cs14-pins {
pins = "GPIO_44";
function = "si";
};
};
&spi0 {
pinctrl-0 = <&si2_pins>;
pinctrl-names = "default";
spi@e {
compatible = "spi-mux";
mux-controls = <&mux>;
#address-cells = <1>;
#size-cells = <0>;
reg = <14>; /* CS14 */
flash@6 {
compatible = "spi-nand";
pinctrl-0 = <&cs14_pins>;
pinctrl-names = "default";
reg = <0x6>; /* SPI2 */
spi-max-frequency = <42000000>;
rx-sample-delay-ns = <7>; /* Tune for speed */
};
};
};
Annotation
- Atlas domain: Architecture Layer / arch/arm64.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.