arch/arm64/boot/dts/microchip/sparx5_pcb125.dts
Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts
File Facts
- System
- Linux kernel
- Corpus path
arch/arm64/boot/dts/microchip/sparx5_pcb125.dts- Extension
.dts- Size
- 1506 bytes
- Lines
- 80
- Domain
- Architecture Layer
- Bucket
- arch/arm64
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
sparx5_pcb_common.dtsi
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
*/
/dts-v1/;
#include "sparx5_pcb_common.dtsi"
/ {
model = "Sparx5 PCB125 Reference Board";
compatible = "microchip,sparx5-pcb125", "microchip,sparx5";
memory@0 {
device_type = "memory";
reg = <0x00000000 0x00000000 0x10000000>;
};
};
&gpio {
emmc_pins: emmc-pins {
/* NB: No "GPIO_35", "GPIO_36", "GPIO_37"
* (N/A: CARD_nDETECT, CARD_WP, CARD_LED)
*/
pins = "GPIO_34", "GPIO_38", "GPIO_39",
"GPIO_40", "GPIO_41", "GPIO_42",
"GPIO_43", "GPIO_44", "GPIO_45",
"GPIO_46", "GPIO_47";
drive-strength = <3>;
function = "emmc";
};
};
&sdhci0 {
status = "okay";
bus-width = <8>;
non-removable;
pinctrl-0 = <&emmc_pins>;
max-frequency = <8000000>;
microchip,clock-delay = <10>;
};
&spi0 {
status = "okay";
spi@0 {
compatible = "spi-mux";
mux-controls = <&mux>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0>; /* CS0 */
flash@9 {
compatible = "jedec,spi-nor";
spi-max-frequency = <8000000>;
reg = <0x9>; /* SPI */
};
};
spi@1 {
compatible = "spi-mux";
mux-controls = <&mux 0>;
#address-cells = <1>;
#size-cells = <0>;
reg = <1>; /* CS1 */
flash@9 {
compatible = "spi-nand";
pinctrl-0 = <&cs1_pins>;
pinctrl-names = "default";
spi-max-frequency = <8000000>;
reg = <0x9>; /* SPI */
};
};
};
Annotation
- Immediate include surface: `sparx5_pcb_common.dtsi`.
- Atlas domain: Architecture Layer / arch/arm64.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.