arch/arm64/boot/dts/nuvoton/ma35d1.dtsi

Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/nuvoton/ma35d1.dtsi

File Facts

System
Linux kernel
Corpus path
arch/arm64/boot/dts/nuvoton/ma35d1.dtsi
Extension
.dtsi
Size
10879 bytes
Lines
436
Domain
Architecture Layer
Bucket
arch/arm64
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2023 Nuvoton Technology Corp.
 * Author: Shan-Chun Hung <schung@nuvoton.com>
 *         Jacky huang <ychuang3@nuvoton.com>
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/nuvoton,ma35d1-clk.h>
#include <dt-bindings/reset/nuvoton,ma35d1-reset.h>

/ {
	compatible = "nuvoton,ma35d1";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a35";
			reg = <0x0 0x0>;
			enable-method = "psci";
			next-level-cache = <&L2_0>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a35";
			reg = <0x0 0x1>;
			enable-method = "psci";
			next-level-cache = <&L2_0>;
		};

		L2_0: l2-cache {
			compatible = "cache";
			cache-level = <2>;
			cache-unified;
			cache-size = <0x80000>;
		};
	};

	psci {
		compatible = "arm,psci-0.2";
		method = "smc";
	};

	gic: interrupt-controller@50801000 {
		compatible = "arm,gic-400";
		reg = <0x0 0x50801000 0 0x1000>, /* GICD */
		      <0x0 0x50802000 0 0x2000>, /* GICC */
		      <0x0 0x50804000 0 0x2000>, /* GICH */
		      <0x0 0x50806000 0 0x2000>; /* GICV */
		#interrupt-cells = <3>;
		interrupt-parent = <&gic>;
		interrupt-controller;
		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0x13) |
			      IRQ_TYPE_LEVEL_HIGH)>;
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
			      IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |

Annotation

Implementation Notes