arch/arm64/boot/dts/nuvoton/ma35d1-som-256m.dts

Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/nuvoton/ma35d1-som-256m.dts

File Facts

System
Linux kernel
Corpus path
arch/arm64/boot/dts/nuvoton/ma35d1-som-256m.dts
Extension
.dts
Size
2613 bytes
Lines
156
Domain
Architecture Layer
Bucket
arch/arm64
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2023 Nuvoton Technology Corp.
 * Author: Shan-Chun Hung <schung@nuvoton.com>
 *         Jacky huang <ychuang3@nuvoton.com>
 */

/dts-v1/;
#include "ma35d1.dtsi"

/ {
	model = "Nuvoton MA35D1-SOM";
	compatible = "nuvoton,ma35d1-som", "nuvoton,ma35d1";

	aliases {
		serial0 = &uart0;
		serial11 = &uart11;
		serial12 = &uart12;
		serial14 = &uart14;
		serial16 = &uart16;
		ethernet0 = &gmac0;
		ethernet1 = &gmac1;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};

	mem: memory@80000000 {
		device_type = "memory";
		reg = <0x00000000 0x80000000 0 0x10000000>; /* 256M DRAM */
	};

	clk_hxt: clock-hxt {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <24000000>;
		clock-output-names = "clk_hxt";
	};
};

&clk {
	assigned-clocks = <&clk CAPLL>,
			  <&clk DDRPLL>,
			  <&clk APLL>,
			  <&clk EPLL>,
			  <&clk VPLL>;
	assigned-clock-rates = <800000000>,
			       <266000000>,
			       <180000000>,
			       <500000000>,
			       <102000000>;
	nuvoton,pll-mode = "integer",
			   "fractional",
			   "integer",
			   "integer",
			   "integer";
};

&pinctrl {
	uart-grp {
		pinctrl_uart0: uart0-pins {
			nuvoton,pins = <4 14 1>,
				       <4 15 1>;
			bias-disable;
			power-source = <1>;
		};

		pinctrl_uart11: uart11-pins {
			nuvoton,pins = <11 0 2>,

Annotation

Implementation Notes