arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi
Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi
File Facts
- System
- Linux kernel
- Corpus path
arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi- Extension
.dtsi- Size
- 18368 bytes
- Lines
- 882
- Domain
- Architecture Layer
- Bucket
- arch/arm64
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
dt-bindings/clock/nuvoton,npcm845-clk.hdt-bindings/interrupt-controller/arm-gic.hdt-bindings/interrupt-controller/irq.h
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2021 Nuvoton Technology tomer.maimon@nuvoton.com
#include <dt-bindings/clock/nuvoton,npcm845-clk.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&gic>;
soc {
#address-cells = <2>;
#size-cells = <2>;
compatible = "simple-bus";
interrupt-parent = <&gic>;
ranges;
gcr: system-controller@f0800000 {
compatible = "nuvoton,npcm845-gcr", "syscon";
reg = <0x0 0xf0800000 0x0 0x1000>;
};
gic: interrupt-controller@dfff9000 {
compatible = "arm,gic-400";
reg = <0x0 0xdfff9000 0x0 0x1000>,
<0x0 0xdfffa000 0x0 0x2000>,
<0x0 0xdfffc000 0x0 0x2000>,
<0x0 0xdfffe000 0x0 0x2000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
#interrupt-cells = <3>;
interrupt-controller;
#address-cells = <0>;
};
};
ahb {
#address-cells = <2>;
#size-cells = <2>;
compatible = "simple-bus";
interrupt-parent = <&gic>;
ranges;
clk: rstc: reset-controller@f0801000 {
compatible = "nuvoton,npcm845-reset";
reg = <0x0 0xf0801000 0x0 0xC4>;
nuvoton,sysgcr = <&gcr>;
#reset-cells = <2>;
clocks = <&refclk>;
#clock-cells = <1>;
};
apb {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
interrupt-parent = <&gic>;
ranges = <0x0 0x0 0xf0000000 0x00300000>,
<0xfff00000 0x0 0xfff00000 0x00016000>;
peci: peci-controller@100000 {
compatible = "nuvoton,npcm845-peci";
reg = <0x100000 0x1000>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk NPCM8XX_CLK_APB3>;
cmd-timeout-ms = <1000>;
status = "disabled";
};
Annotation
- Immediate include surface: `dt-bindings/clock/nuvoton,npcm845-clk.h`, `dt-bindings/interrupt-controller/arm-gic.h`, `dt-bindings/interrupt-controller/irq.h`.
- Atlas domain: Architecture Layer / arch/arm64.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.