arch/arm64/boot/dts/nvidia/tegra186.dtsi

Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/nvidia/tegra186.dtsi

File Facts

System
Linux kernel
Corpus path
arch/arm64/boot/dts/nvidia/tegra186.dtsi
Extension
.dtsi
Size
64114 bytes
Lines
2197
Domain
Architecture Layer
Bucket
arch/arm64
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0
#include <dt-bindings/clock/tegra186-clock.h>
#include <dt-bindings/gpio/tegra186-gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/mailbox/tegra186-hsp.h>
#include <dt-bindings/memory/tegra186-mc.h>
#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
#include <dt-bindings/power/tegra186-powergate.h>
#include <dt-bindings/reset/tegra186-reset.h>
#include <dt-bindings/thermal/tegra186-bpmp-thermal.h>

/ {
	compatible = "nvidia,tegra186";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	misc@100000 {
		compatible = "nvidia,tegra186-misc";
		reg = <0x0 0x00100000 0x0 0xf000>,
		      <0x0 0x0010f000 0x0 0x1000>;
	};

	gpio: gpio@2200000 {
		compatible = "nvidia,tegra186-gpio";
		reg-names = "security", "gpio";
		reg = <0x0 0x2200000 0x0 0x10000>,
		      <0x0 0x2210000 0x0 0x10000>;
		interrupts = <GIC_SPI  47 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI  50 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI  53 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI  56 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI  59 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
		#interrupt-cells = <2>;
		interrupt-controller;
		#gpio-cells = <2>;
		gpio-controller;
		gpio-ranges = <&pinmux 0 0 140>;
	};

	pinmux: pinmux@2430000 {
		compatible = "nvidia,tegra186-pinmux";
		reg = <0x0 0x2430000 0x0 0x15000>;
	};

	ethernet@2490000 {
		compatible = "nvidia,tegra186-eqos",
			     "snps,dwc-qos-ethernet-4.10";
		reg = <0x0 0x02490000 0x0 0x10000>;
		interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* common */
			     <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, /* power */
			     <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, /* rx0 */
			     <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, /* tx0 */
			     <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* rx1 */
			     <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, /* tx1 */
			     <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* rx2 */
			     <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* tx2 */
			     <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* rx3 */
			     <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; /* tx3 */
		clocks = <&bpmp TEGRA186_CLK_AXI_CBB>,
			 <&bpmp TEGRA186_CLK_EQOS_AXI>,
			 <&bpmp TEGRA186_CLK_EQOS_RX>,
			 <&bpmp TEGRA186_CLK_EQOS_TX>,
			 <&bpmp TEGRA186_CLK_EQOS_PTP_REF>;
		clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref";
		resets = <&bpmp TEGRA186_RESET_EQOS>;
		reset-names = "eqos";
		interconnects = <&mc TEGRA186_MEMORY_CLIENT_EQOSR &emc>,
				<&mc TEGRA186_MEMORY_CLIENT_EQOSW &emc>;

Annotation

Implementation Notes