arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi

Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi

File Facts

System
Linux kernel
Corpus path
arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi
Extension
.dtsi
Size
55664 bytes
Lines
1835
Domain
Architecture Layer
Bucket
arch/arm64
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0

#include <dt-bindings/input/input.h>
#include <dt-bindings/input/gpio-keys.h>
#include <dt-bindings/mfd/max77620.h>
#include <dt-bindings/pinctrl/pinctrl-tegra.h>
#include "tegra210.dtsi"

/ {
	aliases {
		serial0 = &uarta;
	};

	chosen {
		bootargs = "earlycon";
		stdout-path = "serial0:115200n8";
	};

	memory@80000000 {
		device_type = "memory";
		reg = <0x0 0x80000000 0x0 0xc0000000>;
	};

	pinmux: pinmux@700008d4 {
		status = "okay";
		pinctrl-names = "boot";
		pinctrl-0 = <&state_boot>;

		state_boot: pinmux {
			pex_l0_rst_n_pa0 {
				nvidia,pins = "pex_l0_rst_n_pa0";
				nvidia,function = "rsvd1";
				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
				nvidia,io-hv = <TEGRA_PIN_DISABLE>;
			};
			pex_l0_clkreq_n_pa1 {
				nvidia,pins = "pex_l0_clkreq_n_pa1";
				nvidia,function = "pe0";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
				nvidia,io-hv = <TEGRA_PIN_ENABLE>;
			};
			pex_wake_n_pa2 {
				nvidia,pins = "pex_wake_n_pa2";
				nvidia,function = "pe";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
				nvidia,io-hv = <TEGRA_PIN_ENABLE>;
			};
			pex_l1_rst_n_pa3 {
				nvidia,pins = "pex_l1_rst_n_pa3";
				nvidia,function = "pe1";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
				nvidia,io-hv = <TEGRA_PIN_ENABLE>;
			};
			pex_l1_clkreq_n_pa4 {
				nvidia,pins = "pex_l1_clkreq_n_pa4";
				nvidia,function = "pe1";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;

Annotation

Implementation Notes