arch/arm64/boot/dts/nvidia/tegra234.dtsi
Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/nvidia/tegra234.dtsi
File Facts
- System
- Linux kernel
- Corpus path
arch/arm64/boot/dts/nvidia/tegra234.dtsi- Extension
.dtsi- Size
- 165312 bytes
- Lines
- 6346
- Domain
- Architecture Layer
- Bucket
- arch/arm64
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
Dependency Surface
dt-bindings/clock/tegra234-clock.hdt-bindings/gpio/tegra234-gpio.hdt-bindings/interrupt-controller/arm-gic.hdt-bindings/mailbox/tegra186-hsp.hdt-bindings/memory/tegra234-mc.hdt-bindings/pinctrl/pinctrl-tegra-io-pad.hdt-bindings/power/tegra234-powergate.hdt-bindings/reset/tegra234-reset.hdt-bindings/thermal/tegra234-bpmp-thermal.hdt-bindings/pinctrl/pinctrl-tegra.h
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: GPL-2.0
#include <dt-bindings/clock/tegra234-clock.h>
#include <dt-bindings/gpio/tegra234-gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/mailbox/tegra186-hsp.h>
#include <dt-bindings/memory/tegra234-mc.h>
#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
#include <dt-bindings/power/tegra234-powergate.h>
#include <dt-bindings/reset/tegra234-reset.h>
#include <dt-bindings/thermal/tegra234-bpmp-thermal.h>
#include <dt-bindings/pinctrl/pinctrl-tegra.h>
/ {
compatible = "nvidia,tegra234";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
aliases {
i2c0 = &gen1_i2c;
i2c1 = &gen2_i2c;
i2c2 = &cam_i2c;
i2c3 = &dp_aux_ch1_i2c;
i2c4 = &bpmp_i2c;
i2c5 = &dp_aux_ch0_i2c;
i2c6 = &dp_aux_ch2_i2c;
i2c7 = &gen8_i2c;
i2c8 = &dp_aux_ch3_i2c;
};
bus@0 {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
misc@100000 {
compatible = "nvidia,tegra234-misc";
reg = <0x0 0x00100000 0x0 0xf000>,
<0x0 0x0010f000 0x0 0x1000>;
};
timer@2080000 {
compatible = "nvidia,tegra234-timer";
reg = <0x0 0x02080000 0x0 0x00121000>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
};
gpio: gpio@2200000 {
compatible = "nvidia,tegra234-gpio";
reg-names = "security", "gpio";
reg = <0x0 0x02200000 0x0 0x10000>,
<0x0 0x02210000 0x0 0x10000>;
Annotation
- Immediate include surface: `dt-bindings/clock/tegra234-clock.h`, `dt-bindings/gpio/tegra234-gpio.h`, `dt-bindings/interrupt-controller/arm-gic.h`, `dt-bindings/mailbox/tegra186-hsp.h`, `dt-bindings/memory/tegra234-mc.h`, `dt-bindings/pinctrl/pinctrl-tegra-io-pad.h`, `dt-bindings/power/tegra234-powergate.h`, `dt-bindings/reset/tegra234-reset.h`.
- Atlas domain: Architecture Layer / arch/arm64.
- Implementation status: atlas-only.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.