arch/arm64/boot/dts/qcom/ipq5332.dtsi

Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/qcom/ipq5332.dtsi

File Facts

System
Linux kernel
Corpus path
arch/arm64/boot/dts/qcom/ipq5332.dtsi
Extension
.dtsi
Size
21309 bytes
Lines
908
Domain
Architecture Layer
Bucket
arch/arm64
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: BSD-3-Clause
/*
 * IPQ5332 device tree source
 *
 * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
 */

#include <dt-bindings/clock/qcom,apss-ipq.h>
#include <dt-bindings/clock/qcom,ipq5332-gcc.h>
#include <dt-bindings/interconnect/qcom,ipq5332.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	interrupt-parent = <&intc>;
	#address-cells = <2>;
	#size-cells = <2>;

	clocks {
		sleep_clk: sleep-clk {
			compatible = "fixed-clock";
			#clock-cells = <0>;
		};

		xo_board: xo-board-clk {
			compatible = "fixed-clock";
			#clock-cells = <0>;
		};
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0>;
			enable-method = "psci";
			next-level-cache = <&l2_0>;
			clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
			operating-points-v2 = <&cpu_opp_table>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x1>;
			enable-method = "psci";
			next-level-cache = <&l2_0>;
			clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
			operating-points-v2 = <&cpu_opp_table>;
		};

		cpu2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x2>;
			enable-method = "psci";
			next-level-cache = <&l2_0>;
			clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
			operating-points-v2 = <&cpu_opp_table>;
		};

		cpu3: cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x3>;
			enable-method = "psci";
			next-level-cache = <&l2_0>;
			clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;

Annotation

Implementation Notes