arch/arm64/boot/dts/qcom/lemans-ride-ethernet-aqr115c.dtsi
Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/qcom/lemans-ride-ethernet-aqr115c.dtsi
File Facts
- System
- Linux kernel
- Corpus path
arch/arm64/boot/dts/qcom/lemans-ride-ethernet-aqr115c.dtsi- Extension
.dtsi- Size
- 3846 bytes
- Lines
- 206
- Domain
- Architecture Layer
- Bucket
- arch/arm64
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
dt-bindings/gpio/gpio.hdt-bindings/interrupt-controller/arm-gic.h
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2023, Linaro Limited
*/
/*
* Ethernet card for Lemans based Ride r3 boards.
* It supports 2x 2.5G - HSGMII (Marvell hsgmii) phy for Main domain
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
aliases {
ethernet0 = ðernet0;
ethernet1 = ðernet1;
};
};
&tlmm {
ethernet0_default: ethernet0-default-state {
ethernet0_mdc: ethernet0-mdc-pins {
pins = "gpio8";
function = "emac0_mdc";
drive-strength = <16>;
bias-pull-up;
};
ethernet0_mdio: ethernet0-mdio-pins {
pins = "gpio9";
function = "emac0_mdio";
drive-strength = <16>;
bias-pull-up;
};
};
};
ðernet0 {
phy-handle = <&hsgmii_phy0>;
phy-mode = "2500base-x";
pinctrl-0 = <ðernet0_default>;
pinctrl-names = "default";
snps,mtl-rx-config = <&mtl_rx_setup>;
snps,mtl-tx-config = <&mtl_tx_setup>;
snps,ps-speed = <1000>;
status = "okay";
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
hsgmii_phy0: phy@8 {
compatible = "ethernet-phy-id31c3.1c33";
reg = <0x8>;
device_type = "ethernet-phy";
interrupts-extended = <&tlmm 7 IRQ_TYPE_EDGE_FALLING>;
reset-gpios = <&pmm8654au_2_gpios 8 GPIO_ACTIVE_LOW>;
reset-assert-us = <11000>;
reset-deassert-us = <70000>;
};
hsgmii_phy1: phy@0 {
compatible = "ethernet-phy-id31c3.1c33";
reg = <0x0>;
device_type = "ethernet-phy";
Annotation
- Immediate include surface: `dt-bindings/gpio/gpio.h`, `dt-bindings/interrupt-controller/arm-gic.h`.
- Atlas domain: Architecture Layer / arch/arm64.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.