arch/arm64/boot/dts/qcom/mahua.dtsi
Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/qcom/mahua.dtsi
File Facts
- System
- Linux kernel
- Corpus path
arch/arm64/boot/dts/qcom/mahua.dtsi- Extension
.dtsi- Size
- 5564 bytes
- Lines
- 301
- Domain
- Architecture Layer
- Bucket
- arch/arm64
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
glymur.dtsi
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
/* Mahua is heavily based on Glymur, with some meaningful differences */
#include "glymur.dtsi"
/delete-node/ &bwmon_cluster2;
/delete-node/ &cluster2_pd;
/delete-node/ &cpu_map_cluster2;
/delete-node/ &cpu12;
/delete-node/ &cpu13;
/delete-node/ &cpu14;
/delete-node/ &cpu15;
/delete-node/ &cpu16;
/delete-node/ &cpu17;
/delete-node/ &cpu_pd12;
/delete-node/ &cpu_pd13;
/delete-node/ &cpu_pd14;
/delete-node/ &cpu_pd15;
/delete-node/ &cpu_pd16;
/delete-node/ &cpu_pd17;
/delete-node/ &cti_wpss;
/delete-node/ &thermal_aoss_6;
/delete-node/ &thermal_aoss_7;
/delete-node/ &thermal_cpu_2_0_0;
/delete-node/ &thermal_cpu_2_0_1;
/delete-node/ &thermal_cpu_2_1_0;
/delete-node/ &thermal_cpu_2_1_1;
/delete-node/ &thermal_cpu_2_2_0;
/delete-node/ &thermal_cpu_2_2_1;
/delete-node/ &thermal_cpu_2_3_0;
/delete-node/ &thermal_cpu_2_3_1;
/delete-node/ &thermal_cpu_2_4_0;
/delete-node/ &thermal_cpu_2_4_1;
/delete-node/ &thermal_cpu_2_5_0;
/delete-node/ &thermal_cpu_2_5_1;
/delete-node/ &thermal_cpuillc_2_1;
/delete-node/ &thermal_cpullc_2_0;
/delete-node/ &thermal_ddr_2;
/delete-node/ &thermal_gpu_3_0;
/delete-node/ &thermal_gpu_3_1;
/delete-node/ &thermal_gpu_3_2;
/delete-node/ &thermal_qmx_2_0;
/delete-node/ &thermal_qmx_2_1;
/delete-node/ &thermal_qmx_2_2;
/delete-node/ &thermal_qmx_2_3;
/delete-node/ &thermal_qmx_2_4;
/delete-node/ &thermal_video_1;
/delete-node/ &tsens6;
/delete-node/ &tsens7;
&aggre1_noc {
compatible = "qcom,mahua-aggre1-noc", "qcom,glymur-aggre1-noc";
};
&aggre2_noc {
compatible = "qcom,mahua-aggre2-noc", "qcom,glymur-aggre2-noc";
};
&aggre3_noc {
compatible = "qcom,mahua-aggre3-noc", "qcom,glymur-aggre3-noc";
};
&aggre4_noc {
compatible = "qcom,mahua-aggre4-noc", "qcom,glymur-aggre4-noc";
};
&clk_virt {
Annotation
- Immediate include surface: `glymur.dtsi`.
- Atlas domain: Architecture Layer / arch/arm64.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.