arch/arm64/boot/dts/qcom/monaco-evk-ifp-mezzanine.dtso
Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/qcom/monaco-evk-ifp-mezzanine.dtso
File Facts
- System
- Linux kernel
- Corpus path
arch/arm64/boot/dts/qcom/monaco-evk-ifp-mezzanine.dtso- Extension
.dtso- Size
- 2863 bytes
- Lines
- 150
- Domain
- Architecture Layer
- Bucket
- arch/arm64
- Inferred role
- Architecture Layer: arch/arm64
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
dt-bindings/gpio/gpio.h
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
/dts-v1/;
/plugin/;
#include <dt-bindings/gpio/gpio.h>
&{/} {
model = "Qualcomm Technologies, Inc. Monaco-EVK IFP Mezzanine";
vreg_0p9: regulator-0v9 {
compatible = "regulator-fixed";
regulator-name = "VREG_0P9";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-always-on;
regulator-boot-on;
};
vreg_1p8: regulator-1v8 {
compatible = "regulator-fixed";
regulator-name = "VREG_1P8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
};
&i2c15 {
#address-cells = <1>;
#size-cells = <0>;
eeprom1: eeprom@52 {
compatible = "giantec,gt24c256c", "atmel,24c256";
reg = <0x52>;
pagesize = <64>;
nvmem-layout {
compatible = "fixed-layout";
#address-cells = <1>;
#size-cells = <1>;
};
};
};
&pcie0 {
iommu-map = <0x0 &pcie_smmu 0x0 0x1>,
<0x100 &pcie_smmu 0x1 0x1>,
<0x208 &pcie_smmu 0x2 0x1>,
<0x210 &pcie_smmu 0x3 0x1>,
<0x218 &pcie_smmu 0x4 0x1>,
<0x300 &pcie_smmu 0x5 0x1>,
<0x400 &pcie_smmu 0x6 0x1>,
<0x500 &pcie_smmu 0x7 0x1>,
<0x501 &pcie_smmu 0x8 0x1>;
};
&pcieport0 {
#address-cells = <3>;
#size-cells = <2>;
pcie@0,0 {
compatible = "pci1179,0623";
reg = <0x10000 0x0 0x0 0x0 0x0>;
Annotation
- Immediate include surface: `dt-bindings/gpio/gpio.h`.
- Atlas domain: Architecture Layer / arch/arm64.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.