arch/arm64/boot/dts/qcom/msm8917.dtsi

Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/qcom/msm8917.dtsi

File Facts

System
Linux kernel
Corpus path
arch/arm64/boot/dts/qcom/msm8917.dtsi
Extension
.dtsi
Size
42015 bytes
Lines
1956
Domain
Architecture Layer
Bucket
arch/arm64
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0-only

#include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
#include <dt-bindings/clock/qcom,gcc-msm8917.h>
#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/thermal/thermal.h>

/ {
	interrupt-parent = <&intc>;

	#address-cells = <2>;
	#size-cells = <2>;

	chosen { };

	clocks {
		sleep_clk: sleep-clk {
			compatible = "fixed-clock";
			#clock-cells = <0>;
		};

		xo_board: xo-board {
			compatible = "fixed-clock";
			#clock-cells = <0>;
		};
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@100 {
			compatible = "arm,cortex-a53";
			reg = <0x100>;
			device_type = "cpu";
			next-level-cache = <&l2_0>;
			enable-method = "psci";
			clocks = <&apcs>;
			operating-points-v2 = <&cpu_opp_table>;
			#cooling-cells = <2>;
			power-domains = <&cpu_pd0>;
			power-domain-names = "psci";

			l2_0: l2-cache {
				compatible = "cache";
				cache-level = <2>;
				cache-unified;
			};
		};

		cpu1: cpu@101 {
			compatible = "arm,cortex-a53";
			reg = <0x101>;
			device_type = "cpu";
			next-level-cache = <&l2_0>;
			enable-method = "psci";
			clocks = <&apcs>;
			operating-points-v2 = <&cpu_opp_table>;
			#cooling-cells = <2>;
			power-domains = <&cpu_pd1>;
			power-domain-names = "psci";
		};

		cpu2: cpu@102 {
			compatible = "arm,cortex-a53";
			reg = <0x102>;
			device_type = "cpu";
			next-level-cache = <&l2_0>;

Annotation

Implementation Notes