arch/arm64/boot/dts/qcom/msm8939.dtsi

Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/qcom/msm8939.dtsi

File Facts

System
Linux kernel
Corpus path
arch/arm64/boot/dts/qcom/msm8939.dtsi
Extension
.dtsi
Size
61943 bytes
Lines
2700
Domain
Architecture Layer
Bucket
arch/arm64
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
 * Copyright (c) 2020-2023, Linaro Limited
 */

#include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
#include <dt-bindings/clock/qcom,gcc-msm8939.h>
#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/interconnect/qcom,msm8939.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/reset/qcom,gcc-msm8939.h>
#include <dt-bindings/soc/qcom,apr.h>
#include <dt-bindings/thermal/thermal.h>

/ {
	interrupt-parent = <&intc>;

	/*
	 * Stock LK wants address-cells/size-cells = 2
	 * A number of our drivers want address/size cells = 1
	 * hence the disparity between top-level and /soc below.
	 */
	#address-cells = <2>;
	#size-cells = <2>;

	clocks {
		xo_board: xo-board {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <19200000>;
		};

		sleep_clk: sleep-clk {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <32764>;
		};
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@100 {
			compatible = "arm,cortex-a53";
			device_type = "cpu";
			enable-method = "spin-table";
			cpu-release-addr = /bits/ 64 <0>;
			reg = <0x100>;
			next-level-cache = <&l2_1>;
			qcom,acc = <&acc0>;
			qcom,saw = <&saw0>;
			cpu-idle-states = <&cpu_sleep_0>;
			clocks = <&apcs1_mbox>;
			#cooling-cells = <2>;
			l2_1: l2-cache {
				compatible = "cache";
				cache-level = <2>;
				cache-unified;
			};
		};

		cpu1: cpu@101 {
			compatible = "arm,cortex-a53";
			device_type = "cpu";
			enable-method = "spin-table";
			cpu-release-addr = /bits/ 64 <0>;
			reg = <0x101>;

Annotation

Implementation Notes