arch/arm64/boot/dts/qcom/msm8953.dtsi

Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/qcom/msm8953.dtsi

File Facts

System
Linux kernel
Corpus path
arch/arm64/boot/dts/qcom/msm8953.dtsi
Extension
.dtsi
Size
55617 bytes
Lines
2484
Domain
Architecture Layer
Bucket
arch/arm64
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: BSD-3-Clause
/* Copyright (c) 2022, The Linux Foundation. All rights reserved. */

#include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
#include <dt-bindings/clock/qcom,gcc-msm8953.h>
#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interconnect/qcom,msm8953.h>
#include <dt-bindings/interconnect/qcom,rpm-icc.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/soc/qcom,apr.h>
#include <dt-bindings/sound/qcom,q6afe.h>
#include <dt-bindings/sound/qcom,q6asm.h>
#include <dt-bindings/thermal/thermal.h>

/ {
	interrupt-parent = <&intc>;

	#address-cells = <2>;
	#size-cells = <2>;

	chosen { };

	clocks {
		sleep_clk: sleep-clk {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <32768>;
		};

		xo_board: xo-board {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <19200000>;
			clock-output-names = "xo";
		};
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0>;
			enable-method = "psci";
			capacity-dmips-mhz = <1024>;
			interconnects = <&bimc MAS_APPS_PROC RPM_ACTIVE_TAG
					 &bimc SLV_EBI RPM_ACTIVE_TAG>;
			next-level-cache = <&l2_0>;
			#cooling-cells = <2>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x1>;
			enable-method = "psci";
			capacity-dmips-mhz = <1024>;
			interconnects = <&bimc MAS_APPS_PROC RPM_ACTIVE_TAG
					 &bimc SLV_EBI RPM_ACTIVE_TAG>;
			next-level-cache = <&l2_0>;
			#cooling-cells = <2>;
		};

		cpu2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";

Annotation

Implementation Notes