arch/arm64/boot/dts/qcom/purwa.dtsi
Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/qcom/purwa.dtsi
File Facts
- System
- Linux kernel
- Corpus path
arch/arm64/boot/dts/qcom/purwa.dtsi- Extension
.dtsi- Size
- 5854 bytes
- Lines
- 259
- Domain
- Architecture Layer
- Bucket
- arch/arm64
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
hamoa.dtsi
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/* X1P42100 is heavily based on hamoa, with some meaningful differences */
#include "hamoa.dtsi"
/delete-node/ &bwmon_cluster0;
/delete-node/ &cluster_pd2;
/delete-node/ &cpu_map_cluster2;
/delete-node/ &cpu8;
/delete-node/ &cpu9;
/delete-node/ &cpu10;
/delete-node/ &cpu11;
/delete-node/ &cpu_pd8;
/delete-node/ &cpu_pd9;
/delete-node/ &cpu_pd10;
/delete-node/ &cpu_pd11;
/delete-node/ &gpu_opp_table;
/delete-node/ &gpu_speed_bin;
/delete-node/ &pcie3_phy;
/delete-node/ &thermal_aoss3;
/delete-node/ &thermal_cpu2_0_btm;
/delete-node/ &thermal_cpu2_0_top;
/delete-node/ &thermal_cpu2_1_btm;
/delete-node/ &thermal_cpu2_1_top;
/delete-node/ &thermal_cpu2_2_btm;
/delete-node/ &thermal_cpu2_2_top;
/delete-node/ &thermal_cpu2_3_btm;
/delete-node/ &thermal_cpu2_3_top;
/delete-node/ &thermal_cpuss2_btm;
/delete-node/ &thermal_cpuss2_top;
/delete-node/ &thermal_gpuss_4;
/delete-node/ &thermal_gpuss_5;
/delete-node/ &thermal_gpuss_6;
/delete-node/ &thermal_gpuss_7;
&gcc {
compatible = "qcom,x1p42100-gcc", "qcom,x1e80100-gcc";
};
&gmu {
compatible = "qcom,adreno-gmu-x145.0", "qcom,adreno-gmu";
};
&gpu {
compatible = "qcom,adreno-43030c00", "qcom,adreno";
nvmem-cells = <&gpu_speed_bin>;
nvmem-cell-names = "speed_bin";
gpu_opp_table: opp-table {
compatible = "operating-points-v2-adreno", "operating-points-v2";
opp-1400000000 {
opp-hz = /bits/ 64 <1400000000>;
opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L4>;
opp-peak-kBps = <16500000>;
qcom,opp-acd-level = <0xa8295ffd>;
opp-supported-hw = <0x3>;
};
opp-1250000000 {
opp-hz = /bits/ 64 <1250000000>;
opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L3>;
opp-peak-kBps = <16500000>;
qcom,opp-acd-level = <0x882a5ffd>;
opp-supported-hw = <0x7>;
};
Annotation
- Immediate include surface: `hamoa.dtsi`.
- Atlas domain: Architecture Layer / arch/arm64.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.