arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso

Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso

File Facts

System
Linux kernel
Corpus path
arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso
Extension
.dtso
Size
5674 bytes
Lines
291
Domain
Architecture Layer
Bucket
arch/arm64
Inferred role
Architecture Layer: arch/arm64
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: BSD-3-Clause
/*
 * Copyright (c) 2025, Qualcomm Innovation Center, Inc. All rights reserved.
*/

/dts-v1/;
/plugin/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/qcom,gcc-sc7280.h>
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>

&{/} {

	vreg_0p9: regulator-0v9 {
		compatible = "regulator-fixed";
		regulator-name = "VREG_0P9";
		regulator-min-microvolt = <900000>;
		regulator-max-microvolt = <900000>;

		regulator-always-on;
		regulator-boot-on;
	};

	vreg_1p8: regulator-1v8 {
		compatible = "regulator-fixed";
		regulator-name = "VREG_1P8";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;

		regulator-always-on;
		regulator-boot-on;
	};
};

&remoteproc_wpss {
       status = "disabled";
};

&spi11 {
	#address-cells = <1>;
	#size-cells = <0>;
	status = "okay";

	st33htpm0: tpm@0 {
		compatible = "st,st33htpm-spi", "tcg,tpm_tis-spi";
		reg = <0>;
		spi-max-frequency = <20000000>;
	};
};

&pcie0 {
	perst-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>;

	pinctrl-0 = <&pcie0_reset_n>, <&pcie0_wake_n>, <&pcie0_clkreq_n>;
	pinctrl-names = "default";

	iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
		    <0x100 &apps_smmu 0x1c01 0x1>,
		    <0x208 &apps_smmu 0x1c04 0x1>,
		    <0x210 &apps_smmu 0x1c05 0x1>,
		    <0x218 &apps_smmu 0x1c06 0x1>,
		    <0x300 &apps_smmu 0x1c07 0x1>,
		    <0x400 &apps_smmu 0x1c08 0x1>,
		    <0x500 &apps_smmu 0x1c09 0x1>,
		    <0x501 &apps_smmu 0x1c10 0x1>;

	status = "okay";
};

&pcie0_phy {

Annotation

Implementation Notes