arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi
Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi
File Facts
- System
- Linux kernel
- Corpus path
arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi- Extension
.dtsi- Size
- 3655 bytes
- Lines
- 174
- Domain
- Architecture Layer
- Bucket
- arch/arm64
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* sc7280 fragment for devices with Chrome bootloader
*
* This file mainly tries to abstract out the memory protections put into
* place by the Chrome bootloader which are different than what's put into
* place by Qualcomm's typical bootloader. It also has a smattering of other
* things that will hold true for any conceivable Chrome design
*
* Copyright 2022 Google LLC.
*/
/*
* Reserved memory changes
*
* Delete all unused memory nodes and define the peripheral memory regions
* required by the setup for Chrome boards.
*/
/delete-node/ &cdsp_mem;
/delete-node/ &domain_idle_states;
/delete-node/ &gpu_zap_mem;
/delete-node/ &gpu_zap_shader;
/delete-node/ &hyp_mem;
/delete-node/ &xbl_mem;
/delete-node/ &reserved_xbl_uefi_log;
/delete-node/ &sec_apps_mem;
/ {
cpus {
domain_idle_states: domain-idle-states {
cluster_sleep_0: cluster-sleep-0 {
compatible = "domain-idle-state";
arm,psci-suspend-param = <0x40003444>;
entry-latency-us = <2752>;
exit-latency-us = <6562>;
min-residency-us = <9926>;
};
};
};
reserved-memory {
camera_mem: memory@8ad00000 {
reg = <0x0 0x8ad00000 0x0 0x500000>;
no-map;
};
};
};
&cluster_pd {
domain-idle-states = <&cluster_sleep_0>;
};
&gpu {
status = "okay";
};
&lpass_aon {
status = "okay";
};
&lpass_core {
status = "okay";
};
&lpass_hm {
status = "okay";
};
&lpass_tlmm {
Annotation
- Atlas domain: Architecture Layer / arch/arm64.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.