arch/arm64/boot/dts/qcom/sc7280-herobrine-lte-sku.dtsi
Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/qcom/sc7280-herobrine-lte-sku.dtsi
File Facts
- System
- Linux kernel
- Corpus path
arch/arm64/boot/dts/qcom/sc7280-herobrine-lte-sku.dtsi- Extension
.dtsi- Size
- 1570 bytes
- Lines
- 62
- Domain
- Architecture Layer
- Bucket
- arch/arm64
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Google Herobrine dts fragment for LTE SKUs
*
* Copyright 2022 Google LLC.
*/
/* Modem setup is different on Chrome setups than typical Qualcomm setup */
/ {
reserved-memory {
mba_mem: memory@9c700000 {
reg = <0x0 0x9c700000 0x0 0x200000>;
no-map;
};
mdata_mem: mpss-metadata {
alloc-ranges = <0x0 0xa0000000 0x0 0x20000000>;
size = <0x0 0x4000>;
no-map;
};
};
};
&ipa {
qcom,gsi-loader = "modem";
status = "okay";
};
&remoteproc_mpss {
compatible = "qcom,sc7280-mss-pil";
reg = <0 0x04080000 0 0x10000>, <0 0x04180000 0 0x48>;
reg-names = "qdsp6", "rmb";
clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
<&gcc GCC_MSS_OFFLINE_AXI_CLK>,
<&gcc GCC_MSS_SNOC_AXI_CLK>,
<&rpmhcc RPMH_PKA_CLK>,
<&rpmhcc RPMH_CXO_CLK>;
clock-names = "iface", "offline", "snoc_axi", "pka", "xo";
iommus = <&apps_smmu 0x124 0x0>, <&apps_smmu 0x488 0x7>;
interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>;
memory-region = <&mba_mem>, <&mpss_mem>, <&mdata_mem>;
firmware-name = "qcom/sc7280-herobrine/modem/mba.mbn",
"qcom/sc7280-herobrine/modem/qdsp6sw.mbn";
resets = <&aoss_reset AOSS_CC_MSS_RESTART>,
<&pdc_reset PDC_MODEM_SYNC_RESET>;
reset-names = "mss_restart", "pdc_reset";
qcom,halt-regs = <&tcsr_1 0x3000 0x5000 0x8000 0x13000>;
qcom,ext-regs = <&tcsr_2 0x10000 0x10004 &tcsr_1 0x6004 0x6008>;
qcom,qaccept-regs = <&tcsr_1 0x3030 0x3040 0x3020>;
status = "okay";
};
/* Increase the size from 2.5MB to 8MB */
&rmtfs_mem {
reg = <0x0 0x9c900000 0x0 0x800000>;
};
Annotation
- Atlas domain: Architecture Layer / arch/arm64.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.