arch/arm64/boot/dts/qcom/sdm630.dtsi

Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/qcom/sdm630.dtsi

File Facts

System
Linux kernel
Corpus path
arch/arm64/boot/dts/qcom/sdm630.dtsi
Extension
.dtsi
Size
66984 bytes
Lines
2805
Domain
Architecture Layer
Bucket
arch/arm64
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: BSD-3-Clause
/*
 * Copyright (c) 2020, Konrad Dybcio <konradybcio@gmail.com>
 * Copyright (c) 2020, AngeloGioacchino Del Regno <kholk11@gmail.com>
 */

#include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
#include <dt-bindings/clock/qcom,gcc-sdm660.h>
#include <dt-bindings/clock/qcom,gpucc-sdm660.h>
#include <dt-bindings/clock/qcom,mmcc-sdm660.h>
#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/firmware/qcom,scm.h>
#include <dt-bindings/interconnect/qcom,sdm660.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/thermal/thermal.h>
#include <dt-bindings/soc/qcom,apr.h>

/ {
	interrupt-parent = <&intc>;

	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
		mmc1 = &sdhc_1;
		mmc2 = &sdhc_2;
	};

	chosen { };

	clocks {
		xo_board: xo-board {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <19200000>;
			clock-output-names = "xo_board";
		};

		sleep_clk: sleep-clk {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <32764>;
			clock-output-names = "sleep_clk";
		};
	};

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		cpu0: cpu@100 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0 0x100>;
			enable-method = "psci";
			cpu-idle-states = <&perf_cpu_sleep_0
						&perf_cpu_sleep_1
						&perf_cluster_sleep_0
						&perf_cluster_sleep_1
						&perf_cluster_sleep_2>;
			capacity-dmips-mhz = <1126>;
			#cooling-cells = <2>;
			next-level-cache = <&l2_1>;
			l2_1: l2-cache {
				compatible = "cache";
				cache-level = <2>;
				cache-unified;
			};

Annotation

Implementation Notes