arch/arm64/boot/dts/qcom/sdm636.dtsi
Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/qcom/sdm636.dtsi
File Facts
- System
- Linux kernel
- Corpus path
arch/arm64/boot/dts/qcom/sdm636.dtsi- Extension
.dtsi- Size
- 624 bytes
- Lines
- 29
- Domain
- Architecture Layer
- Bucket
- arch/arm64
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
sdm660.dtsi
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2020, AngeloGioacchino Del Regno <kholk11@gmail.com>
* Copyright (c) 2020, Konrad Dybcio <konradybcio@gmail.com>
* Copyright (c) 2020, Martin Botka <martin.botka1@gmail.com>
*/
#include "sdm660.dtsi"
/delete-node/ &remoteproc_cdsp;
/delete-node/ &cdsp_smmu;
/delete-node/ &cdsp_region;
/ {
/delete-node/ smp2p-cdsp;
reserved-memory {
buffer_mem: tzbuffer@94a00000 {
reg = <0x0 0x94a00000 0x00 0x100000>;
no-map;
};
};
};
&adreno_gpu {
compatible = "qcom,adreno-509.0", "qcom,adreno";
/* Adreno 509 shares the frequency table with 512 */
};
Annotation
- Immediate include surface: `sdm660.dtsi`.
- Atlas domain: Architecture Layer / arch/arm64.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.