arch/arm64/boot/dts/qcom/sdm670.dtsi

Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/qcom/sdm670.dtsi

File Facts

System
Linux kernel
Corpus path
arch/arm64/boot/dts/qcom/sdm670.dtsi
Extension
.dtsi
Size
63438 bytes
Lines
2378
Domain
Architecture Layer
Bucket
arch/arm64
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0
/*
 * SDM670 SoC device tree source, adapted from SDM845 SoC device tree
 *
 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
 * Copyright (c) 2022, Richard Acayan. All rights reserved.
 */

#include <dt-bindings/clock/qcom,camcc-sdm845.h>
#include <dt-bindings/clock/qcom,dispcc-sdm845.h>
#include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
#include <dt-bindings/clock/qcom,gcc-sdm845.h>
#include <dt-bindings/clock/qcom,gpucc-sdm845.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/dma/qcom-gpi.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interconnect/qcom,osm-l3.h>
#include <dt-bindings/interconnect/qcom,sdm670-rpmh.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/phy/phy-qcom-qusb2.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>

/ {
	interrupt-parent = <&intc>;

	#address-cells = <2>;
	#size-cells = <2>;

	aliases { };

	chosen { };

	clocks {
		sleep_clk: sleep-clk {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <32764>;
		};

		xo_board: xo-board {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <38400000>;
		};
	};

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "qcom,kryo360";
			reg = <0x0 0x0>;
			enable-method = "psci";
			capacity-dmips-mhz = <610>;
			dynamic-power-coefficient = <203>;
			qcom,freq-domain = <&cpufreq_hw 0>;
			operating-points-v2 = <&cpu0_opp_table>;
			interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>,
					<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
			power-domains = <&cpu_pd0>;
			power-domain-names = "psci";
			next-level-cache = <&l2_0>;
			l2_0: l2-cache {
				compatible = "cache";
				next-level-cache = <&l3_0>;
				cache-level = <2>;
				cache-unified;

Annotation

Implementation Notes