arch/arm64/boot/dts/qcom/sm8750.dtsi

Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/qcom/sm8750.dtsi

File Facts

System
Linux kernel
Corpus path
arch/arm64/boot/dts/qcom/sm8750.dtsi
Extension
.dtsi
Size
159082 bytes
Lines
6890
Domain
Architecture Layer
Bucket
arch/arm64
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: BSD-3-Clause
/*
 * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
 */

#include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,sm8750-cambistmclkcc.h>
#include <dt-bindings/clock/qcom,sm8750-camcc.h>
#include <dt-bindings/clock/qcom,sm8750-dispcc.h>
#include <dt-bindings/clock/qcom,sm8750-gcc.h>
#include <dt-bindings/clock/qcom,sm8750-tcsr.h>
#include <dt-bindings/clock/qcom,sm8750-videocc.h>
#include <dt-bindings/dma/qcom-gpi.h>
#include <dt-bindings/firmware/qcom,scm.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interconnect/qcom,icc.h>
#include <dt-bindings/interconnect/qcom,sm8750-rpmh.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>
#include <dt-bindings/phy/phy-qcom-qmp.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/soc/qcom,gpr.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
#include <dt-bindings/thermal/thermal.h>

/ {
	interrupt-parent = <&intc>;

	#address-cells = <2>;
	#size-cells = <2>;

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "qcom,oryon";
			reg = <0x0 0x0>;
			enable-method = "psci";
			next-level-cache = <&l2_0>;
			power-domains = <&cpu_pd0>, <&scmi_dvfs 0>;
			power-domain-names = "psci", "perf";
			#cooling-cells = <2>;

			l2_0: l2-cache {
				compatible = "cache";
				cache-level = <2>;
				cache-unified;
			};
		};

		cpu1: cpu@100 {
			device_type = "cpu";
			compatible = "qcom,oryon";
			reg = <0x0 0x100>;
			enable-method = "psci";
			next-level-cache = <&l2_0>;
			power-domains = <&cpu_pd1>, <&scmi_dvfs 0>;
			power-domain-names = "psci", "perf";
			#cooling-cells = <2>;
		};

		cpu2: cpu@200 {
			device_type = "cpu";
			compatible = "qcom,oryon";
			reg = <0x0 0x200>;

Annotation

Implementation Notes