arch/arm64/boot/dts/realtek/kent.dtsi

Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/realtek/kent.dtsi

File Facts

System
Linux kernel
Corpus path
arch/arm64/boot/dts/realtek/kent.dtsi
Extension
.dtsi
Size
4089 bytes
Lines
187
Domain
Architecture Layer
Bucket
arch/arm64
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0
/*
 * Realtek Kent SoC family
 *
 * Copyright (c) 2024 Realtek Semiconductor Corp.
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>

/ {
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
		serial0 = &uart0;
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI  9 IRQ_TYPE_LEVEL_HIGH>;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a78";
			reg = <0x0>;
			enable-method = "psci";
			next-level-cache = <&l2_0>;
			dynamic-power-coefficient = <454>;
			#cooling-cells = <2>;

			l2_0: l2-cache {
				compatible = "cache";
				cache-level = <2>;
				cache-line-size = <64>;
				cache-sets = <256>;
				cache-size = <0x40000>;
				cache-unified;
				next-level-cache = <&l3>;
			};
		};

		cpu1: cpu@100 {
			device_type = "cpu";
			compatible = "arm,cortex-a78";
			reg = <0x100>;
			enable-method = "psci";
			next-level-cache = <&l2_1>;
			dynamic-power-coefficient = <454>;
			#cooling-cells = <2>;

			l2_1: l2-cache {
				compatible = "cache";
				cache-level = <2>;
				cache-line-size = <64>;
				cache-sets = <256>;
				cache-size = <0x40000>;
				cache-unified;
				next-level-cache = <&l3>;
			};

Annotation

Implementation Notes