arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi

Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi

File Facts

System
Linux kernel
Corpus path
arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi
Extension
.dtsi
Size
6437 bytes
Lines
334
Domain
Architecture Layer
Bucket
arch/arm64
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright 2020, Compass Electronics Group, LLC
 */

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/versaclock.h>

/ {
	memory@48000000 {
		device_type = "memory";
		/* first 128MB is reserved for secure area. */
		reg = <0x0 0x48000000 0x0 0x78000000>;
	};

	osc_32k: osc_32k {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <32768>;
		clock-output-names = "osc_32k";
	};

	reg_1p8v: regulator-1p8v {
		compatible = "regulator-fixed";
		regulator-name = "fixed-1.8V";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
		regulator-boot-on;
		regulator-always-on;
	};

	reg_3p3v: regulator-3p3v {
		compatible = "regulator-fixed";
		regulator-name = "fixed-3.3V";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-boot-on;
		regulator-always-on;
	};

	wlan_pwrseq: wlan_pwrseq {
		compatible = "mmc-pwrseq-simple";
		reset-gpios = <&pca9654 1 GPIO_ACTIVE_LOW>;
		clocks = <&osc_32k>;
		clock-names = "ext_clock";
		post-power-on-delay-ms = <80>;
	};
};

&avb {
	pinctrl-0 = <&avb_pins>;
	pinctrl-names = "default";
	phy-mode = "rgmii-rxid";
	phy-handle = <&phy0>;
	rx-internal-delay-ps = <1800>;
	tx-internal-delay-ps = <2000>;
	clocks = <&cpg CPG_MOD 812>, <&versaclock5 4>;
	clock-names = "fck", "refclk";
	status = "okay";

	phy0: ethernet-phy@0 {
		compatible = "ethernet-phy-id0022.1640";
		reg = <0>;
		interrupts-extended = <&gpio2 11 IRQ_TYPE_LEVEL_LOW>;
		reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
	};
};

&extal_clk {
	clock-frequency = <16666666>;

Annotation

Implementation Notes