arch/arm64/boot/dts/renesas/r8a77980.dtsi

Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/renesas/r8a77980.dtsi

File Facts

System
Linux kernel
Corpus path
arch/arm64/boot/dts/renesas/r8a77980.dtsi
Extension
.dtsi
Size
48116 bytes
Lines
1730
Domain
Architecture Layer
Bucket
arch/arm64
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0
/*
 * Device Tree Source for the R-Car V3H (R8A77980) SoC
 *
 * Copyright (C) 2018 Renesas Electronics Corp.
 * Copyright (C) 2018 Cogent Embedded, Inc.
 */

#include <dt-bindings/clock/r8a77980-cpg-mssr.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/r8a77980-sysc.h>

/ {
	compatible = "renesas,r8a77980";
	#address-cells = <2>;
	#size-cells = <2>;
	interrupt-parent = <&gic>;

	/* External CAN clock - to be overridden by boards that provide it */
	can_clk: can {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <0>;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		a53_0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0>;
			clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>;
			power-domains = <&sysc R8A77980_PD_CA53_CPU0>;
			next-level-cache = <&L2_CA53>;
			enable-method = "psci";
		};

		a53_1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <1>;
			clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>;
			power-domains = <&sysc R8A77980_PD_CA53_CPU1>;
			next-level-cache = <&L2_CA53>;
			enable-method = "psci";
		};

		a53_2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <2>;
			clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>;
			power-domains = <&sysc R8A77980_PD_CA53_CPU2>;
			next-level-cache = <&L2_CA53>;
			enable-method = "psci";
		};

		a53_3: cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <3>;
			clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>;
			power-domains = <&sysc R8A77980_PD_CA53_CPU3>;
			next-level-cache = <&L2_CA53>;
			enable-method = "psci";
		};

Annotation

Implementation Notes