arch/arm64/boot/dts/renesas/r8a77995.dtsi
Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/renesas/r8a77995.dtsi
File Facts
- System
- Linux kernel
- Corpus path
arch/arm64/boot/dts/renesas/r8a77995.dtsi- Extension
.dtsi- Size
- 43767 bytes
- Lines
- 1499
- Domain
- Architecture Layer
- Bucket
- arch/arm64
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
dt-bindings/clock/r8a77995-cpg-mssr.hdt-bindings/interrupt-controller/arm-gic.hdt-bindings/power/r8a77995-sysc.h
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the R-Car D3 (R8A77995) SoC
*
* Copyright (C) 2016 Renesas Electronics Corp.
* Copyright (C) 2017 Glider bvba
*/
#include <dt-bindings/clock/r8a77995-cpg-mssr.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/r8a77995-sysc.h>
/ {
compatible = "renesas,r8a77995";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&gic>;
/*
* The external audio clocks are configured as 0 Hz fixed frequency
* clocks by default.
* Boards that provide audio clocks should override them.
*/
audio_clk_a: audio_clk_a {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
audio_clk_b: audio_clk_b {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
/* External CAN clock - to be overridden by boards that provide it */
can_clk: can {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
a53_0: cpu@0 {
compatible = "arm,cortex-a53";
reg = <0x0>;
device_type = "cpu";
power-domains = <&sysc R8A77995_PD_CA53_CPU0>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
};
L2_CA53: cache-controller-1 {
compatible = "cache";
power-domains = <&sysc R8A77995_PD_CA53_SCU>;
cache-unified;
cache-level = <2>;
};
};
extal_clk: extal {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overridden by the board */
clock-frequency = <0>;
bootph-all;
};
Annotation
- Immediate include surface: `dt-bindings/clock/r8a77995-cpg-mssr.h`, `dt-bindings/interrupt-controller/arm-gic.h`, `dt-bindings/power/r8a77995-sysc.h`.
- Atlas domain: Architecture Layer / arch/arm64.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.