arch/arm64/boot/dts/renesas/r9a07g043u.dtsi

Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi

File Facts

System
Linux kernel
Corpus path
arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
Extension
.dtsi
Size
8583 bytes
Lines
276
Domain
Architecture Layer
Bucket
arch/arm64
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
 * Device Tree Source for the RZ/G2UL SoC
 *
 * Copyright (C) 2022 Renesas Electronics Corp.
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>

#define SOC_PERIPHERAL_IRQ(nr)		GIC_SPI nr

#include "r9a07g043.dtsi"

/ {
	interrupt-parent = <&gic>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			compatible = "arm,cortex-a55";
			reg = <0>;
			device_type = "cpu";
			#cooling-cells = <2>;
			next-level-cache = <&L3_CA55>;
			enable-method = "psci";
			clocks = <&cpg CPG_CORE R9A07G043_CLK_I>;
			operating-points-v2 = <&cluster0_opp>;
		};

		L3_CA55: cache-controller-0 {
			compatible = "cache";
			cache-unified;
			cache-size = <0x40000>;
			cache-level = <3>;
		};
	};

	pmu {
		compatible = "arm,cortex-a55-pmu";
		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
	};

	psci {
		compatible = "arm,psci-1.0", "arm,psci-0.2";
		method = "smc";
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
		interrupt-names = "sec-phys", "phys", "virt", "hyp-phys",
				  "hyp-virt";
	};
};

&soc {
	cru: video@10830000 {
		compatible = "renesas,r9a07g043-cru", "renesas,rzg2l-cru";
		reg = <0 0x10830000 0 0x400>;
		clocks = <&cpg CPG_MOD R9A07G043_CRU_VCLK>,
			 <&cpg CPG_MOD R9A07G043_CRU_PCLK>,
			 <&cpg CPG_MOD R9A07G043_CRU_ACLK>;
		clock-names = "video", "apb", "axi";
		interrupts = <SOC_PERIPHERAL_IRQ(167) IRQ_TYPE_LEVEL_HIGH>,

Annotation

Implementation Notes