arch/arm64/boot/dts/renesas/r9a08g045s33-smarc-pmod1-type-3a.dtso

Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/renesas/r9a08g045s33-smarc-pmod1-type-3a.dtso

File Facts

System
Linux kernel
Corpus path
arch/arm64/boot/dts/renesas/r9a08g045s33-smarc-pmod1-type-3a.dtso
Extension
.dtso
Size
1237 bytes
Lines
49
Domain
Architecture Layer
Bucket
arch/arm64
Inferred role
Architecture Layer: arch/arm64
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
 * Device Tree Source for the RZ/G3S SMARC Carrier II EVK PMOD parts
 *
 * Copyright (C) 2024 Renesas Electronics Corp.
 *
 *
 * [Connection]
 *
 * SMARC Carrier II EVK
 * +--------------------------------------------+
 * |PMOD1_3A (PMOD1 PIN HEADER)			|
 * |	SCIF1_CTS# (pin1)  (pin7)  PMOD1_GPIO10	|
 * |	SCIF1_TXD  (pin2)  (pin8)  PMOD1_GPIO11	|
 * |	SCIF1_RXD  (pin3)  (pin9)  PMOD1_GPIO12	|
 * |	SCIF1_RTS# (pin4)  (pin10) PMOD1_GPIO13	|
 * |	GND	   (pin5)  (pin11) GND		|
 * |	PWR_PMOD1  (pin6)  (pin12) GND		|
 * +--------------------------------------------+
 *
 * The following switches should be set as follows for SCIF1:
 * - SW_CONFIG2:  ON
 * - SW_OPT_MUX4: ON
 */

/dts-v1/;
/plugin/;

#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
#include "rzg3s-smarc-switches.h"

&pinctrl {
	scif1_pins: scif1-pins {
		pinmux = <RZG2L_PORT_PINMUX(14, 0, 1)>, /* TXD */
			 <RZG2L_PORT_PINMUX(14, 1, 1)>, /* RXD */
			 <RZG2L_PORT_PINMUX(16, 0, 1)>, /* CTS# */
			 <RZG2L_PORT_PINMUX(16, 1, 1)>; /* RTS# */
	};
};

#if SW_CONFIG3 == SW_ON && SW_OPT_MUX4 == SW_ON
&scif1 {
	pinctrl-names = "default";
	pinctrl-0 = <&scif1_pins>;
	uart-has-rtscts;
	status = "okay";
};
#endif

Annotation

Implementation Notes