arch/arm64/boot/dts/renesas/r9a09g047.dtsi

Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/renesas/r9a09g047.dtsi

File Facts

System
Linux kernel
Corpus path
arch/arm64/boot/dts/renesas/r9a09g047.dtsi
Extension
.dtsi
Size
53731 bytes
Lines
1690
Domain
Architecture Layer
Bucket
arch/arm64
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
 * Device Tree Source for the RZ/G3E SoC
 *
 * Copyright (C) 2024 Renesas Electronics Corp.
 */

#include <dt-bindings/clock/renesas,r9a09g047-cpg.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	compatible = "renesas,r9a09g047";
	#address-cells = <2>;
	#size-cells = <2>;
	interrupt-parent = <&gic>;

	audio_extal_clk: audio-clk {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		/* This value must be overridden by the board */
		clock-frequency = <0>;
	};

	/*
	 * The default cluster table is based on the assumption that the PLLCA55 clock
	 * frequency is set to 1.7GHz. The PLLCA55 clock frequency can be set to
	 * 1.7/1.6/1.5/1.1 GHz based on the BOOTPLLCA_0/1 pins (and additionally can be
	 * clocked to 1.8GHz as well). The table below should be overridden in the board
	 * DTS based on the PLLCA55 clock frequency.
	 */
	cluster0_opp: opp-table-0 {
		compatible = "operating-points-v2";

		opp-1700000000 {
			opp-hz = /bits/ 64 <1700000000>;
			opp-microvolt = <900000>;
			clock-latency-ns = <300000>;
		};
		opp-850000000 {
			opp-hz = /bits/ 64 <850000000>;
			opp-microvolt = <800000>;
			clock-latency-ns = <300000>;
		};
		opp-425000000 {
			opp-hz = /bits/ 64 <425000000>;
			opp-microvolt = <800000>;
			clock-latency-ns = <300000>;
		};
		opp-212500000 {
			opp-hz = /bits/ 64 <212500000>;
			opp-microvolt = <800000>;
			clock-latency-ns = <300000>;
			opp-suspend;
		};
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			compatible = "arm,cortex-a55";
			reg = <0>;
			device_type = "cpu";
			next-level-cache = <&L3_CA55>;
			enable-method = "psci";
			clocks = <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK0>;
			#cooling-cells = <2>;
			operating-points-v2 = <&cluster0_opp>;
		};

Annotation

Implementation Notes