arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
File Facts
- System
- Linux kernel
- Corpus path
arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts- Extension
.dts- Size
- 5794 bytes
- Lines
- 293
- Domain
- Architecture Layer
- Bucket
- arch/arm64
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
dt-bindings/gpio/gpio.hdt-bindings/input/input.hdt-bindings/pinctrl/renesas,r9a09g047-pinctrl.hr9a09g047e57.dtsirzg3e-smarc-som.dtsirenesas-smarc2.dtsi
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Source for the RZ/G3E SMARC EVK board
*
* Copyright (C) 2024 Renesas Electronics Corp.
*/
/dts-v1/;
/* Switch selection settings */
#define SW_GPIO8_CAN0_STB 0
#define SW_GPIO9_CAN1_STB 0
#define SW_LCD_EN 0
#define SW_PDM_EN 0
#define SW_SER0_PMOD 1
#define SW_SER2_EN 1
#define SW_SD0_DEV_SEL 0
#define SW_SDIO_M2E 0
#define PMOD_GPIO4 0
#define PMOD_GPIO6 0
#define PMOD_GPIO7 0
#define KEY_1_GPIO RZG3E_GPIO(3, 1)
#define KEY_2_GPIO RZG3E_GPIO(8, 4)
#define KEY_3_GPIO RZG3E_GPIO(8, 5)
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/pinctrl/renesas,r9a09g047-pinctrl.h>
#include "r9a09g047e57.dtsi"
#include "rzg3e-smarc-som.dtsi"
#include "renesas-smarc2.dtsi"
/ {
model = "Renesas SMARC EVK version 2 based on r9a09g047e57";
compatible = "renesas,smarc2-evk", "renesas,rzg3e-smarcm",
"renesas,r9a09g047e57", "renesas,r9a09g047";
aliases {
i2c0 = &i2c0;
serial0 = &rsci4;
serial1 = &rsci9;
serial2 = &rsci2;
serial3 = &scif0;
mmc1 = &sdhi1;
};
vqmmc_sd1_pvdd: regulator-vqmmc-sd1-pvdd {
compatible = "regulator-gpio";
regulator-name = "SD1_PVDD";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
gpios = <&pinctrl RZG3E_GPIO(1, 5) GPIO_ACTIVE_HIGH>;
gpios-states = <0>;
states = <3300000 0>, <1800000 1>;
};
};
&canfd {
pinctrl-0 = <&canfd_pins>;
pinctrl-names = "default";
#if (!SW_PDM_EN)
channel1 {
status = "okay";
#if (!SW_LCD_EN) && (SW_GPIO9_CAN1_STB)
phys = <&can_transceiver1>;
#endif
};
Annotation
- Immediate include surface: `dt-bindings/gpio/gpio.h`, `dt-bindings/input/input.h`, `dt-bindings/pinctrl/renesas,r9a09g047-pinctrl.h`, `r9a09g047e57.dtsi`, `rzg3e-smarc-som.dtsi`, `renesas-smarc2.dtsi`.
- Atlas domain: Architecture Layer / arch/arm64.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.