arch/arm64/boot/dts/renesas/r9a09g077.dtsi

Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/renesas/r9a09g077.dtsi

File Facts

System
Linux kernel
Corpus path
arch/arm64/boot/dts/renesas/r9a09g077.dtsi
Extension
.dtsi
Size
41354 bytes
Lines
1429
Domain
Architecture Layer
Bucket
arch/arm64
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
 * Device Tree Source for the RZ/T2H SoC
 *
 * Copyright (C) 2025 Renesas Electronics Corp.
 */

#include <dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>

/* The IRQ_NS lines start at offset 16 in the ICU interrupt space */
#define RZT2H_IRQ0	16
#define RZT2H_IRQ1	17
#define RZT2H_IRQ2	18
#define RZT2H_IRQ3	19
#define RZT2H_IRQ4	20
#define RZT2H_IRQ5	21
#define RZT2H_IRQ6	22
#define RZT2H_IRQ7	23
#define RZT2H_IRQ8	24
#define RZT2H_IRQ9	25
#define RZT2H_IRQ10	26
#define RZT2H_IRQ11	27
#define RZT2H_IRQ12	28
#define RZT2H_IRQ13	29
#define RZT2H_IRQ14	30
#define RZT2H_IRQ15	31

/ {
	compatible = "renesas,r9a09g077";
	#address-cells = <2>;
	#size-cells = <2>;
	interrupt-parent = <&gic>;

	cluster0_opp: opp-table-0 {
		compatible = "operating-points-v2";

		opp-600000000 {
			opp-hz = /bits/ 64 <600000000>;
		};
		opp-1200000000 {
			opp-hz = /bits/ 64 <1200000000>;
		};
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			compatible = "arm,cortex-a55";
			reg = <0>;
			device_type = "cpu";
			next-level-cache = <&L3_CA55>;
			enable-method = "psci";
			clocks = <&cpg CPG_CORE R9A09G077_CLK_CA55C0>;
			#cooling-cells = <2>;
			operating-points-v2 = <&cluster0_opp>;
		};

		cpu1: cpu@100 {
			compatible = "arm,cortex-a55";
			reg = <0x100>;
			device_type = "cpu";
			next-level-cache = <&L3_CA55>;
			enable-method = "psci";
			clocks = <&cpg CPG_CORE R9A09G077_CLK_CA55C1>;
			#cooling-cells = <2>;
			operating-points-v2 = <&cluster0_opp>;
		};

Annotation

Implementation Notes