arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts

Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts

File Facts

System
Linux kernel
Corpus path
arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts
Extension
.dts
Size
11330 bytes
Lines
442
Domain
Architecture Layer
Bucket
arch/arm64
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
 * Device Tree Source for the RZ/N2H EVK board
 *
 * Copyright (C) 2025 Renesas Electronics Corp.
 */

/dts-v1/;

#include <dt-bindings/input/input.h>

#include "r9a09g087m44.dtsi"

/*
 * SD0 can be connected to either eMMC (U33) or SD card slot CN21
 * Lets by default enable the eMMC, note we need the below SW settings
 * for eMMC. Also ensure that JP23 pins 5 and 6 are connected with a jumper
 * to provide the SD0 power supply when using eMMC.
 * DSW5[1] = ON; DSW5[2] = ON
 * DSW17[5] = OFF; DSW17[6] = ON
 *
 * To enable SD card and disable eMMC on SDHI0 disable the below macro
 * and set the below switch settings. Also ensure that JP23 pins 3 and 4 are
 * connected with a jumper to provide the SD0 power supply when using an SD card.
 * DSW5[1] = OFF; DSW5[2] = ON
 * P22_6 = SD0_WP; DSW15[1] = OFF; DSW15[2] = ON
 * P22_5 = SD0_CD; DSW15[3] = OFF; DSW15[4] = ON
 * P02_6 = SD0_IOVS; DSW17[5] = OFF; DSW17[6] = ON
 * P02_5 = SD0_PWEN; DSW17[7] = OFF; DSW17[8] = ON
 */
#define SD0_EMMC       1
#define SD0_SD		(!SD0_EMMC)

/*
 * To enable CANFD interface disable both eMMC and SD card on SDHI0 by
 * setting SD0_EMMC and SD0_SD macros to 0 as pins P12_0 and P12_1
 * will be used for CANFD interface.
 */
#define CANFD_ENABLE	(!SD0_EMMC && !SD0_SD)

/*
 * P17_4 = SD1_CD; DSW5[3] = ON; DSW19[1] = OFF; DSW19[2] = ON
 * P08_6 = SD1_IOVS; DSW5[3] = ON
 * To enable proper operation in 1.8V modes, JP21 must have pins 2 and 3
 * connected by the jumper. This connects SD1 power-supply control IC output
 * back to VCC1833_7.
 */
#define SD1_MICRO_SD	1

/*
 * USB Pin Configuration:
 *
 * This board is equipped with three USB connectors: Type-A (CN7), Mini-B
 * (CN8), and Micro-AB (CN9). The RZ/N2H SoC has a single USB channel, so
 * either the USB host interface or the USB function interface can be used,
 * but not both simultaneously when using the CN7 and CN8 connectors.
 *
 * By default, the Type-A (CN7) and Mini-B (CN8) connectors are enabled.
 * Configure the switches as follows:
 *   - P02_2 - P02_3 (control signals for USB power supply): DSW2[6] = OFF;
 *     - P02_2 (used for VBUSEN): DSW14[5] = OFF; DSW14[6] = ON
 *     - P02_3 (used for USB_OVRCUR): DSW14[1] = OFF; DSW14[2] = ON
 *   - USB_VBUSIN (used for VBUS of CN8): DSW16[1] = OFF; DSW16[2] = ON
 *   - USB_VBUSEN (used for USB_HF_VBUSEN): DSW16[3] = OFF; DSW16[4] = ON
 *
 * To enable the Micro-AB (CN9) USB OTG connector, set the following macro
 * to 1 and configure the switches as follows:
 *   - P02_2 - P02_3 (control signals for USB power supply): DSW2[6] = OFF;
 *     - P02_2 (used for VBUSEN): DSW14[5] = OFF; DSW14[6] = ON
 *     - P02_3 (used for USB_OVRCUR): DSW14[1] = OFF; DSW14[2] = ON

Annotation

Implementation Notes