arch/arm64/boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi
Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi
File Facts
- System
- Linux kernel
- Corpus path
arch/arm64/boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi- Extension
.dtsi- Size
- 3932 bytes
- Lines
- 169
- Domain
- Architecture Layer
- Bucket
- arch/arm64
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
dt-bindings/gpio/gpio.hdt-bindings/pinctrl/rzg2l-pinctrl.h
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Source for the RZ/{G2L,V2L} SMARC pincontrol parts
*
* Copyright (C) 2021 Renesas Electronics Corp.
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
&pinctrl {
pinctrl-0 = <&sound_clk_pins>;
pinctrl-names = "default";
can0_pins: can0 {
pinmux = <RZG2L_PORT_PINMUX(10, 1, 2)>, /* TX */
<RZG2L_PORT_PINMUX(11, 0, 2)>; /* RX */
};
/* SW7 should be at position 2->3 so that GPIO8_CAN0_STB line is activated */
can0-stb-hog {
gpio-hog;
gpios = <RZG2L_GPIO(42, 2) GPIO_ACTIVE_HIGH>;
output-low;
line-name = "can0_stb";
};
can1_pins: can1 {
pinmux = <RZG2L_PORT_PINMUX(12, 1, 2)>, /* TX */
<RZG2L_PORT_PINMUX(13, 0, 2)>; /* RX */
};
/* SW8 should be at position 2->3 so that GPIO9_CAN1_STB line is activated */
can1-stb-hog {
gpio-hog;
gpios = <RZG2L_GPIO(42, 3) GPIO_ACTIVE_HIGH>;
output-low;
line-name = "can1_stb";
};
gpt_pins: gpt {
pinmux = <RZG2L_PORT_PINMUX(43, 0, 2)>, /* GTIOC4A */
<RZG2L_PORT_PINMUX(43, 1, 2)>; /* GTIOC4B */
};
i2c0_pins: i2c0 {
pins = "RIIC0_SDA", "RIIC0_SCL";
input-enable;
};
i2c1_pins: i2c1 {
pins = "RIIC1_SDA", "RIIC1_SCL";
input-enable;
};
i2c3_pins: i2c3 {
pinmux = <RZG2L_PORT_PINMUX(18, 0, 3)>, /* SDA */
<RZG2L_PORT_PINMUX(18, 1, 3)>; /* SCL */
};
mtu3_pins: mtu3 {
mtu3-ext-clk-input-pin {
pinmux = <RZG2L_PORT_PINMUX(48, 0, 4)>, /* MTCLKA */
<RZG2L_PORT_PINMUX(48, 1, 4)>; /* MTCLKB */
};
mtu3-pwm {
pinmux = <RZG2L_PORT_PINMUX(44, 0, 4)>, /* MTIOC3A */
<RZG2L_PORT_PINMUX(44, 1, 4)>, /* MTIOC3B */
<RZG2L_PORT_PINMUX(44, 2, 4)>, /* MTIOC3C */
Annotation
- Immediate include surface: `dt-bindings/gpio/gpio.h`, `dt-bindings/pinctrl/rzg2l-pinctrl.h`.
- Atlas domain: Architecture Layer / arch/arm64.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.