arch/arm64/boot/dts/rockchip/px30-engicam-ctouch2.dtsi
Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/rockchip/px30-engicam-ctouch2.dtsi
File Facts
- System
- Linux kernel
- Corpus path
arch/arm64/boot/dts/rockchip/px30-engicam-ctouch2.dtsi- Extension
.dtsi- Size
- 578 bytes
- Lines
- 31
- Domain
- Architecture Layer
- Bucket
- arch/arm64
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
px30-engicam-common.dtsi
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2020 Engicam srl
* Copyright (c) 2020 Amarula Solutions
* Copyright (c) 2020 Amarula Solutions(India)
*/
#include "px30-engicam-common.dtsi"
&pinctrl {
bt {
bt_enable_h: bt-enable-h {
rockchip,pins = <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
sdio-pwrseq {
wifi_enable_h: wifi-enable-h {
rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&sdio_pwrseq {
reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
};
&vcc3v3_btreg {
gpios = <&gpio1 RK_PC3 GPIO_ACTIVE_HIGH>;
};
Annotation
- Immediate include surface: `px30-engicam-common.dtsi`.
- Atlas domain: Architecture Layer / arch/arm64.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.