arch/arm64/boot/dts/rockchip/rk3328.dtsi

Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/rockchip/rk3328.dtsi

File Facts

System
Linux kernel
Corpus path
arch/arm64/boot/dts/rockchip/rk3328.dtsi
Extension
.dtsi
Size
50955 bytes
Lines
2035
Domain
Architecture Layer
Bucket
arch/arm64
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
 */

#include <dt-bindings/clock/rk3328-cru.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/power/rk3328-power.h>
#include <dt-bindings/soc/rockchip,boot-mode.h>
#include <dt-bindings/thermal/thermal.h>

/ {
	compatible = "rockchip,rk3328";

	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
		gpio0 = &gpio0;
		gpio1 = &gpio1;
		gpio2 = &gpio2;
		gpio3 = &gpio3;
		serial0 = &uart0;
		serial1 = &uart1;
		serial2 = &uart2;
		i2c0 = &i2c0;
		i2c1 = &i2c1;
		i2c2 = &i2c2;
		i2c3 = &i2c3;
	};

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0 0x0>;
			clocks = <&cru ARMCLK>;
			#cooling-cells = <2>;
			cpu-idle-states = <&CPU_SLEEP>;
			dynamic-power-coefficient = <120>;
			enable-method = "psci";
			operating-points-v2 = <&cpu0_opp_table>;
			i-cache-size = <0x8000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <128>;
			next-level-cache = <&l2_cache>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0 0x1>;
			clocks = <&cru ARMCLK>;
			#cooling-cells = <2>;
			cpu-idle-states = <&CPU_SLEEP>;
			dynamic-power-coefficient = <120>;
			enable-method = "psci";
			operating-points-v2 = <&cpu0_opp_table>;
			i-cache-size = <0x8000>;
			i-cache-line-size = <64>;

Annotation

Implementation Notes