arch/arm64/boot/dts/rockchip/rk3566-orangepi-3b-v1.1.dts
Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/rockchip/rk3566-orangepi-3b-v1.1.dts
File Facts
- System
- Linux kernel
- Corpus path
arch/arm64/boot/dts/rockchip/rk3566-orangepi-3b-v1.1.dts- Extension
.dts- Size
- 548 bytes
- Lines
- 30
- Domain
- Architecture Layer
- Bucket
- arch/arm64
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
rk3566-orangepi-3b.dtsi
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/dts-v1/;
#include "rk3566-orangepi-3b.dtsi"
/ {
model = "Xunlong Orange Pi 3B v1.1";
compatible = "xunlong,orangepi-3b-v1.1", "xunlong,orangepi-3b", "rockchip,rk3566";
};
&pmu_io_domains {
vccio5-supply = <&vcc_3v3>;
};
&gmac1 {
phy-handle = <&rgmii_phy1>;
status = "okay";
};
&mdio1 {
rgmii_phy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
reset-assert-us = <20000>;
reset-deassert-us = <50000>;
reset-gpios = <&gpio3 RK_PC2 GPIO_ACTIVE_LOW>;
};
};
Annotation
- Immediate include surface: `rk3566-orangepi-3b.dtsi`.
- Atlas domain: Architecture Layer / arch/arm64.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.