arch/arm64/boot/dts/rockchip/rk3566-qnap-ts133.dts
Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/rockchip/rk3566-qnap-ts133.dts
File Facts
- System
- Linux kernel
- Corpus path
arch/arm64/boot/dts/rockchip/rk3566-qnap-ts133.dts- Extension
.dts- Size
- 1465 bytes
- Lines
- 72
- Domain
- Architecture Layer
- Bucket
- arch/arm64
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
rk3566.dtsirk3568-qnap-tsx33.dtsi
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
* Copyright (c) 2024 Heiko Stuebner <heiko@sntech.de>
*/
/dts-v1/;
#include "rk3566.dtsi"
#include "rk3568-qnap-tsx33.dtsi"
/ {
model = "Qnap TS-133-2G NAS System 1-Bay";
compatible = "qnap,ts133", "rockchip,rk3566";
aliases {
ethernet0 = &gmac1;
};
};
&gmac1 {
assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>;
assigned-clock-rates = <0>, <125000000>;
clock_in_out = "output";
phy-handle = <&rgmii_phy0>;
phy-mode = "rgmii-id";
pinctrl-names = "default";
pinctrl-0 = <&gmac1m1_miim
&gmac1m1_tx_bus2
&gmac1m1_rx_bus2
&gmac1m1_rgmii_clk
&gmac1m1_rgmii_bus>;
status = "okay";
};
&mcu {
compatible = "qnap,ts133-mcu";
};
&mdio1 {
rgmii_phy0: ethernet-phy@3 {
/* Motorcomm YT8521 phy */
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x3>;
pinctrl-0 = <ð_phy0_reset_pin>;
pinctrl-names = "default";
reset-assert-us = <10000>;
reset-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_LOW>;
};
};
&pinctrl {
gmac1 {
eth_phy0_reset_pin: eth-phy0-reset-pin {
rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
};
/* connected to usb_host1_xhci */
&usb2phy0_host {
phy-supply = <&vcc5v0_otg>;
status = "okay";
};
/* USB3 port on backside */
&usb_host1_xhci {
dr_mode = "host";
status = "okay";
Annotation
- Immediate include surface: `rk3566.dtsi`, `rk3568-qnap-tsx33.dtsi`.
- Atlas domain: Architecture Layer / arch/arm64.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.